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參數(shù)資料
| 型號： | M38073E4-XXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 0.80 MM PITCH, PLASTIC, QFP-80 |
| 文件頁數(shù)： | 42/75頁 |
| 文件大?。?/td> | 1279K |
| 代理商： | M38073E4-XXXFP |
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46
MITSUBISHI MICROCOMPUTERS
3807 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(2) Watchdog timer H count source selection bit operation
Bit 7 of the watchdog timer control register (address 001716) permits
selecting a watchdog timer H count source. When this bit is set to
"0", the count source becomes the underflow signal of watchdog timer
L. The detection time is set then to f(XIN)=131.072 ms at 8 MHz
frequency and f(XCIN)=32.768 s at 32 kHz frequency.
When this bit is set to "1", the count source becomes the signal
divided by 16 for f(XIN) (or f(XCIN)). The detection time in this case is
set to f(XIN)=512
s at 8 MHz frequency and f(XCIN)=128 ms at 32
KHz frequency. This bit is cleared to "0" after resetting.
(3) Operation of STP instruction disable bit
Bit 6 of the watchdog timer control register (address 001716) permits
disabling the STP instruction when the watchdog timer is in opera-
tion.
When this bit is "0", the STP instruction is enabled.
When this bit is "1", the STP instruction is disabled.
Once the STP instruction is executed, an internal resetting takes place.
When this bit is set to "1", it cannot be rewritten to "0" by program.
This bit is cleared to "0" after resetting.
Watchdog Timer
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, because
of a software run-away). The watchdog timer consists of an 8-bit
watchdog timer L and a 8-bit watchdog timer H.
qStandard operation of watchdog timer
When any data is not written into the watchdog timer control register
(address 001716) after resetting, the watchdog timer is in the stop
state. The watchdog timer starts to count down by writing an optional
value into the watchdog timer control register (address 001716) and
an internal resetting takes place at an underflow of the watchdog
timer H.
Accordingly, programming is usually performed so that writing to the
watchdog timer control register (address 001716) may be started
before an underflow. When the watchdog timer control register
(address 001716) is read, the values of the 6 high-order bits of the
watchdog timer H, STP instruction disable bit, and watchdog timer H
count source selection bit are read.
(1) Initial value of watchdog timer
At reset or writing to the watchdog timer control register (address
001716), each watchdog timer H and L is set to "FF16."
XIN
Data bus
XCIN
"10"
"00"
"01"
Main clock division
ratio selection bits
(Note)
"0"
"1"
1/16
Watchdog timer H count
source selection bit
Reset
circuit
STP instruction disable bit
Watchdog timer H (8)
“FF16” is set when
watchdog timer
control register is
written to.
Internal reset
RESET
Watchdog timer L (8)
Note: Either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of CPU mode register.
STP instruction
“FF16” is set when
watchdog timer
control register is
written to.
Fig. 48. Block diagram of Watchdog timer
b0
STP instruction disable bit
0: STP instruction enabled
1: STP instruction disabled
Watchdog timer H count source selection bit
0: Watchdog timer L underflow
1: f(XIN)/16 or f(XCIN)/16
Watchdog timer H (for read-out of high-order 6 bit)
Watchdog timer control register
(WDTCON : address 001716)
b7
Fig. 49. Structure of Watchdog timer control register
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