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參數(shù)資料
| 型號： | M38073E4-XXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 0.80 MM PITCH, PLASTIC, QFP-80 |
| 文件頁數(shù)： | 39/75頁 |
| 文件大?。?/td> | 1279K |
| 代理商： | M38073E4-XXXFP |
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43
3807 Group
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A-D Converter
[A-D Conversion Register] AD (address 003516)
The A-D conversion register is a read-only register that contains the
result of an A-D conversion. When reading this register during an
A-D conversion, the previous conversion result is read.
[A-D Control Register] ADCON
The A-D control register controls the A-D conversion process. Bits 0
to 3 of this register select specific analog input pins. Bit 4 signals the
completion of an A-D conversion. The value of this bit remains at "0"
during an A-D conversion, then changes to "1" when the A-D conver-
sion is completed. Writing "0" to this bit starts the A-D conversion.
When bit 6, which is the AD external trigger valid bit, is set to "1", this
bit enables A-D conversion at a falling edge of an ADT input. Set
ports which is also used as ADT pins to input when using an A-D
external trigger. Bit 5 is the ADVREF input switch bit. Writing "1" to
this bit, this bit always causes ADVREF connection. Writing "0" to this
bit causes ADVREF connection only during A-D conversion and cut
off when A-D conversion is completed.
[Comparison Voltage Generator]
The comparison voltage generator divides the voltage between AVSS
and ADVREF by 256, and outputs the divided voltages.
[Channel Selector]
The channel selector selects one of the input ports AN12 to AN0 and
inputs it to the comparator.
[Comparator and Control Circuit]
The comparator and control circuit compares an analog input
voltage with the comparison voltage and stores the result in the A-D
conversion register. When an A-D conversion is completed, the
control circuit sets the AD conversion completion bit and the AD
conversion interrupt request bit to "1."
Note that the comparator is constructed linked to a capacitor, so set
f(XIN) to at least 500kHz during A-D conversion. Use a CPU system
clock dividing the main clock XIN as the internal clock
φ.
sNote
When the A-D external trigger is invalidated by the AD external
trigger valid bit, any interrupt request is not generated at a fall of the
ADT input. When the AD external trigger valid bit is set to "1" before-
hand, A-D conversion is not started by writing "0" into the AD conver-
sion completion bit and "0" is not written into the AD conversion
completion bit. Do not set "0" in the AD conversion completion bit
concurrently with the timing at which the AD external trigger valid bit
is rewritten. Put an interval of at least 50 cycles to more of the
internal clock
φ between a start of A-D conversion and the next start
of A-D conversion.
A-D control register
(ADCON : address 003416)
Analog input pin selection bit
0000: P73/SRDY2/ADT/AN0
0001: P74/AN1
0010: P75/AN2
0011: P76/AN3
0100: P77/AN4
0101: P60/AN5
0110: P61/AN6
0111: P62/AN7
1000: P63/CMPIN/AN8
1001: P64/CMPREF/AN9
1010: P65/DAVREF/AN10
1011: P80/DA3/AN11
1100: P81/DA4/AN12
AD conversion completion bit
0: Conversion in progress
1: Conversion completed
ADVREF input switch bit
0: OFF
1: ON
AD external trigger valid bit
0: A-D external trigger invalid
1: A-D external trigger valid
Interrupt source selection bit
0: Interrupt request at A-D
conversion completed
1: Interrupt request at ADT
input falling
b7
b0
A-D control register
Channel
selector
A-D control circuit
A-D conversion register
Resistor ladder
AVSS ADVREF
Comparator
ADT/A-D interrupt request
b7
b0
Data bus
4
8
P73/SRDY2/ADT/AN0
P74/AN1
P75/AN2
P76/AN3
P77/AN4
P60/AN5
P61/AN6
P62/AN7
P63/CMPIN/AN8
P64/CMPREF/AN9
P65/DAVREF/AN10
P80/DA3/AN11
P81/DA4/AN12
Fig. 42. Structure of A-D control register
Fig. 43. Block diagram of A-D converter
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