參數(shù)資料
型號： M38037M8H-XXXWG
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8.4 MHz, MICROCONTROLLER, PBGA64
封裝： 6 X 6 MM, 0.65 MM PITCH, PLASTIC, FLGA-64
文件頁數(shù)： 49/111頁
文件大?。?/td> 1205K
代理商： M38037M8H-XXXWG
Rev.3.02
Nov 05, 2004
page 42 of 108
3803 Group (Spec. H)
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
SERIAL I/O
Serial I/O1
Serial I/O1 can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer is also provided for
baud rate generation.
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O1 mode can be selected by setting
the serial I/O1 mode selection bit of the serial I/O1 control register
(bit 6 of address 001A16) to “1”.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the transmit/receive buffer register.
Fig. 33 Block diagram of clock synchronous serial I/O1
Fig. 34 Operation of clock synchronous serial I/O1
1/4
F/F
P46/SCLK1
Serial I/O1 status register
Serial I/O1 control register
P47/SRDY1
P44/RXD1
P45/TXD1
Receive buffer register 1
Address 001816
Receive shift register 1
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Clock control circuit
Shift clock
Serial I/O1 synchronous
clock selection bit
Frequency division ratio 1/(n+1)
Baud rate generator 1
Address 001C16
BRG count source selection bit
Clock control circuit
Falling-edge detector
Transmit buffer register 1
Data bus
Address 001816
Shift clock
Transmit shift completion flag (TSC)
Transmit buffer empty flag (TBE)
Transmit interrupt request (TI)
Transmit interrupt source selection bit
Address 001916
Data bus
Address 001A16
Transmit shift register 1
f(XIN)
(f(XCIN) in low-speed mode)
D7
D0
D1
D2
D3
D4
D5
D6
D0
D1
D2
D3
D4
D5
D6
RBF = 1
TSC = 1
TBE = 0
TBE = 1
TSC = 0
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TxD1
Serial input RxD1
Write pulse to receive/transmit
buffer register (address 001816)
Overrun error (OE)
detection
Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after the
transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1
control register.
2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data
is output continuously from the TxD pin.
3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Receive enable signal SRDY1
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