(3/7)
Corrections and Supplementary Explanation for M37906MxX Datasheet (Rev.C) No.3
Memory map of M37906M8C-XXXFP/SP (Single-chip
mode)
Page 8
Page
Error
Correction
Page 20,
Fig. 11
Processor mode register
0
10
2
43
5
Processor mode bits
00 : Single-chip mode
Processor mode register
0
10
2
43
5
Processor mode bits
00 : Single-chip mode
00
Page 12,
3. Interrupt disable
flag (I)
all interrupts except watchdog timer, NMI, and soft-
ware interrupt
(Line 3)
all interrupts except watchdog timer and software
interrupts
(Line 3)
Page 21,
Left column
Line 3
Reset is also handled as a type of interrupt in this
section, too.
Reset is also handled as an interrupt source in this
section, too.
Page 21,
Left column
Line 21
The position to which pin INT3 is to be allocated can be
selected
The position where pin INT3/RTPTRG0 is allocated can be
selected
Page 22,
Fig. 13
(Interrupt control register bit configuration for INT3–INT7)
10
2
43
5
Interrupt priority level select bits
(Notes 1, 2)
Interrupt request bit
(Interrupt control register bit configuration for INT3–INT7)
10
2
43
5
Interrupt priority level select bits
(Note 1)
Interrupt request bit (Note 2)
Page 40,
Right column
Lines 5, 6
This bit is cleared to “0” by inputting falling edge to the
INT4 pin, by reset, or by clearing with instructions.
This bit is cleared to “0” by inputting a falling edge to
pin P6OUTCUT, by reset, or by executing instructions.
Page 39,
Fig. 43
Reset
INT4
DQ
R
Waveform output control bit
(bit 7 at addresss A616)
Reset
P6OUTCUT
DQ
R
Waveform output control bit
(bit 7 at addresss A616)
Page 43,
Fig. 47
position-data-retain function control
register
10
2
43
5
Retained trigger’s polarity select bit
Page 44,
Left column
Last line
count start flag to “1”, and they stop it when clearing
that flag to “0”.
count start bit to “1”, and they stop it when clearing
that bit to “0”.
Page 44,
Fig. 48
Reset
INT4
DQ
R
Reset
P6OUTCUT
DQ
R
Waveform output control bit 1
(bit 7 at addresss A616)
Waveform output control bit 1
(bit 7 at addresss A616)
Page 45,
Fig. 49
Waveform output control register
10
2
43
5
Waveform output mode register
10
2
43
5
Page 46,
Right column
Line 35
the pulse to which pulse width modulation is applied
output port
the pulse to which pulse width modulation has been
applied output port
Page 46,
Right column
Line 51
by reset or clearing with instructions.
by reset or by executing instructions.
position-data-retain function control
register
10
2
43
5
Retain-trigger polarity select bit
Page 43,
Left column
Line 7
Retained data can be read out
Retain data can be read out
Memory map of M37906M6C-XXXFP/SP (Single-chip
mode)
Page 7