參數(shù)資料
型號(hào)： M37906M4H-XXXSP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PDIP42
封裝： 0.600 INCH, 1.78 MM PITCH, PLASTIC, SDIP-42
文件頁(yè)數(shù)： 100/101頁(yè)
文件大小： 766K
代理商： M37906M4H-XXXSP
(4/7)
Corrections and Supplementary Explanation for M37906MxX Datasheet (Rev.C) No.4
Page
Error
Correction
Page 46,
Right column
Last line
by inputting a falling edge to an external interrupt pin,
INT4.
by inputting a falling edge to pin P6OUTCUT.
Page 47,
Left column
Line 45
by inputting a falling edge to an external interrupt pin,
INT4, or clearing with instructions.
by inputting a falling edge to pin P6OUTCUT, or by
executing instructions.
Page 49,
Left column
Line 5
shown in Figure 55 are used to determine whether to
use port P8 as a
shown in Figure 55 are used to determine whether to
use port P1 as a
Page 49,
Fig. 55
UART0 Transmit/Receive mode register
UART1 Transmit/Receive mode register
10
2
43
5
Serial I/O mode select bits
000 : Serial I/O is invalid. (Port P8 fun-
ctions as a programmable I/O port.)
UART0 Transmit/Receive mode register
UART1 Transmit/Receive mode register
10
2
43
5
Serial I/O mode select bits
000 : Serial I/O is invalid. (Port P1 fun-
ctions as a programmable I/O port.)
Page 69,
Lines 6, 7
an input pin when it is “0”.
When a pin is programmed for output, the data
an input pin when it is “0”.
Also, each bit of the port P6 direction register can be
cleared to “0” by inputting a falling edge to pin
P6OUTCUT or by executing instructions.
When a pin is programmed for output, the data
Page 59,
Table 8
Pin P10/CTS0/RTS0 (Note 1)
Functions
CTS2
Pin P11/
P11 or CLK0
Pin P10/CTS0/RTS0 (Note 1)
Functions
CTS0
Pin P11/
P11 or CLK0
Page 63,
Operation mode
Line 8
the comparator function select register is “0” and
the comparator function select register 0 is “0” and
Page 63,
Operation mode
Last line
the comparator result register.
the comparator result register 0.
Page 70,
Fig. 76
[Inside dotted-line included]
P20/TA4 OUT, P22/TA9 OUT,
P60/TA0 OUT/W/RTP00,
P61/TA0 IN/V/RTP01,
P62/TA1 OUT/U/RTP02,
P63/TA1 IN/W/RTP03,
P64/TA2 OUT/V/RTP10,
P65/TA2 IN/U/RTP11
[Inside dotted-line included]
P20/TA4 OUT, P22/TA9 OUT
The block diagram for port P6 pins (the 3rd block dia-
gram) is added.
Page 72,
Fig. 79
Comparison result register 0 (DE16)
Comparator result register 0 (DE16)
0016
Page 74,
Left column
Lines 2 to 6
and Figure 81 shows a circuit example with an external
ceramic resonator or quartz crystal oscillator. The cons-
tants such as capacitance etc. depend on a resonator/
oscillator.
and Figure 81 shows a circuit example with an external
ceramic resonator or quartz-crystal oscillator. The cons-
tants such as capacitance etc. depend on an oscillator.
Page 73,
Fig. 78
000
0
Debug control register 1 (8116)
(Note 2)
00
000
0
Debug control register 1 (8116)
00
Page 74,
Left column
Line 22
enable bit (bit 1 of the clock control register; See
Figure 85.),
enable bit (bit 1 of the clock control register 0; See
Figure 85.),
Page 74,
Fig. 81
Fig. 81 Circuit example with external ceramic resonator
or quartz crystal oscillator
Fig. 81 Circuit example with external ceramic resonator
or quartz-crystal oscillator
Page 74,
Fig. 83
Fig. 83 Circuit example with pin VCONT and PLL circuit
Fig. 83 Circuit example of connection with pin V CONT
when PLL circuit used
Page 75,
Left column
Lines 7, 27
Right column
Lines 15, 10, 21
the clock control register
the clock control register 0
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