49
M37906M4C-XXXFP, M37906M4C-XXXSP, M37906M4H-XXXFP
M37906M4H-XXXSP, M37906M6C-XXXFP, M37906M6C-XXXSP
M37906M8C-XXXFP, M37906M8C-XXXSP
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Som
e param
etric
lim
its are
subject
to change.
16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Serial I/O mode select bits
0 0 0 : Serial I/O is invalid. (Port P1 functions as a programmable I/O port.)
0 0 1 : Clock synchronous
1 0 0 : 7-bit UART
1 0 1 : 8-bit UART
1 1 0 : 9-bit UART
Internal/External clock select bit
0 : Internal clock
1 : External clock
Stop bit length select bit (Valid in UART mode.)
0 : 1 stop bit
1 : 2 stop bits
Odd/Even parity select bit (Valid in UART mode with the parity enable bit = “1”.) (Note)
0 : Odd parity
1 : Even parity
Parity enable bit (Valid in UART mode) (Note)
0 : No parity
1 : With parity
Sleep select bit (Valid in UART mode) (Note)
0 : No sleep
1 : Sleep
76543210
UART 0 Transmit/Receive mode register
UART 1 Transmit/Receive mode register
Addresses
3016
3816
Note: In the clock synchronous serial I/O mode, bits 4 to 6 are invalid. (Each of them may be “0” or “1”.) Furthermore, fix bit 7 to “0”.
SERIAL I/O PORTS
Two independent serial I/O ports are provided. Figure 54 shows a
block diagram of the serial I/O ports.
Bits 0 through 2 of the UARTi(i = 0, 1) transmit/receive mode register
shown in Figure 55 are used to determine whether to use port P1 as
a programmable I/O port, clock synchronous serial I/O port, or asyn-
chronous (UART) serial I/O port which uses start and stop bits.
Figures 56 and 57 show the block diagrams of the receiver/transmit-
ter.
Figure 58 shows the bit configuration of the UARTi transmit/receive
control register.
Each communication method is described below.
Fig. 55 Bit configuration of UARTi transmit/receive mode register
Fig. 54 Block diagram of serial I/O port
UARTi receive register
TXDi
RXDi
Receive
control
circuit
Transmit
control
circuit
UARTi transmit register
1/16 divider
1/2 divider
1/(n + 1) divider
1/16 divider
Transfer clock
UARTi
transmit buffer register
UART
Clock synchronous
Clock synchronous (when internal clock selected)
BRG count source select bits
f2
f16
f64
f512
Clock synchronous
(Internal clock)
UART
D7 D6 D5 D4 D3 D2 D1
UARTi
receive buffer register
D0
D7
D8
D6 D5 D4 D3 D2 D1 D0
0D8
0
BRGi
UART0 (Addresses 3316, 3216)
UART1 (Addresses 3B16, 3A16)
UART0 (Addresses 3716, 3616)
UART1 (Addresses 3F16, 3E16)
CTSi/RTSi
Clock synchronous
(External clock)
n = a value set into the UARTi baud rate register (BRGi)
CLKi
CTSi
CTSi/CLKi
Data bus (even)
Data bus (odd)
Bit converter
Data bus (odd)
Data bus (even)
Bit converter