參數(shù)資料
型號(hào)： M37906M4C-XXXSP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PDIP42
封裝： 0.600 INCH, 1.78 MM PITCH, PLASTIC, SDIP-42
文件頁數(shù)： 16/101頁
文件大?。?/td> 766K
代理商： M37906M4C-XXXSP
21
M37906M4C-XXXFP, M37906M4C-XXXSP, M37906M4H-XXXFP
M37906M4H-XXXSP, M37906M6C-XXXFP, M37906M6C-XXXSP
M37906M8C-XXXFP, M37906M8C-XXXSP
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Som
e param
etric
lim
its are
subject
to change.
16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
INTERRUPTS
Table 3 shows the interrupt sources and the corresponding interrupt
vector addresses. Reset is also handled as an interrupt source in
this section, too.
DBC and BRK instruction are interrupts used only for debugging.
Therefore, do not use these interrupts.
Interrupts other than reset, watchdog timer, zero divide, and address
matching detection all have interrupt control registers. Table 4 shows
the addresses of the interrupt control registers and Figure 13 shows
the bit configuration of the interrupt control register.
The interrupt request bit is automatically cleared by the hardware
during reset or when processing an interrupt. Also, interrupt request
bits except for that of a watchdog timer interrupt can be cleared by
software.
An INTi (i = 3 to 7) interrupt request is generated by an external in-
put.
INTi is an external interrupt; whether to cause an interrupt at the in-
put level (level sense) or at the edge (edge sense) can be selected
with the level/edge select bit. Furthermore, the polarity of the inter-
rupt input can be selected with the polarity select bit.
The position where pin INT3/RTPTRG0 is allocated can be selected
by the pin INT3/RTPTRG0 select bit (bit 3 of the port P2 pin function
control register; address AE16), as shown in Figure 17.
When using the following pins as external interrupt input pins, be
sure to clear the direction registers of the corresponding multiplexed
ports to “0”: pins P27/INT3, P55/INT5, P56/INT6, and P57(P74)/INT7.
When the external interrupt input read register (address 9516), which
is shown in Figure 12, is read out, the status of pins INT3 through
INT7 can directly be read.
Timer and UART interrupts are described in the respective section.
The priority of interrupts when multiple interrupt requests are caused
simultaneously is partially fixed by hardware, but, it can also be ad-
justed by software as shown in Figure 14.
The hardware priority is fixed as the following:
reset > watchdog timer > other interrupts
Interrupts
Timer A9
Timer A8
Timer A7
Timer A6
Timer A5
INT7 external interrupt
INT6 external interrupt
INT5 external interrupt
Address matching detection interrupt
INT4 external interrupt
INT3 external interrupt
A-D conversion
UART1 transmit
UART1 receive
UART0 transmit
UART0 receive
Timer B2
Timer B1
Timer B0
Timer A4
Timer A3
Timer A2
Timer A1
Timer A0
Watchdog timer
DBC (Do not select.)
Break instruction (Do not select.)
Zero divide
Reset
Table 3. Interrupt sources and interrupt vector addresses
Vector addresses
00FFB816
00FFB916
00FFBA16
00FFBB16
00FFBC16
00FFBD16
00FFBE16
00FFBF16
00FFC016
00FFC116
00FFC216
00FFC316
00FFC416
00FFC516
00FFC616
00FFC716
00FFCA16
00FFCB16
00FFD016
00FFD116
00FFD216
00FFD316
00FFD416
00FFD516
00FFD616
00FFD716
00FFD816
00FFD916
00FFDA16
00FFDB16
00FFDC16
00FFDD16
00FFDE16
00FFDF16
00FFE016
00FFE116
00FFE216
00FFE316
00FFE416
00FFE516
00FFE616
00FFE716
00FFE816
00FFE916
00FFEA16
00FFEB16
00FFEC16
00FFED16
00FFF616
00FFF716
00FFF816
00FFF916
00FFFA16
00FFFB16
00FFFC16
00FFFD16
00FFFE16
00FFFF16
Fig. 12 Bit configuration of external interrupt input read register
76543210
Undefined at read.
INT3 read bit
INT4 read bit
INT5 read bit
INT6 read bit
INT7 read bit
External interrupt input read register
Address
9516
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參數(shù)描述
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