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| 型號(hào)： | M37902FCCHP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 26 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁(yè)數(shù)： | 47/143頁(yè) |
| 文件大?。?/td> | 1148K |
| 代理商： | M37902FCCHP |
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Corrections and Supplementary Explanation for M37902FxC Datasheet (REV.B) NO.8
Page
Error
Correction
(8/11)
Page 81,
Fig. 83,
bits 1 and 0
1
Waveform output select bits
11 : RTP1 and RTP0 selected
When pulse mode 0 is selected:
RTP1 and RTP1
Page 86,
Fig. 91,
bits 2 to 0
Address/Port switch select bits
0 0 0 :
210
0
1
Waveform output select bits
11 : RTP1 and RTP0 selected
When pulse mode 0 is selected:
RTP1 and RTP0
0
Address/Port switch bits
0 0 0 :
21 0
Page 80,
Left column,
Line 15
The D-A output enable bit is cleared to“0” at reset.
The contents of the corresponding D-A output enable bit
and D-A register are cleared to “0” at reset.
Page 80,
Right column,
Line 1
with pin D-Ai.with pin D-Ai.
Also, when not using the D-A converter, be sure to clear
the contents of the corresponding D-A output enable bit
and D-A register to “0”.
[Inside dotted-line not included]
P40/ALE, P41/
φ1, P42/HLDA,
Page 87,
Fig. 89,
2nd diagram
[Inside dotted-line not included]
P40/ALE, P41/
φ1, P42/HLDA,
Port latch
Output
Port latch
Output (Internal peripheral devices)
Page 88,
Fig. 90,
3rd diagram
[Inside dotted-line not included]
P77/AN7/ADTRG/DA1/(INT2)
[Inside dotted-line included]
P77/AN7/ADTRG/DA1/(INT2)
Page 82,
Right column,
Lines 1 to 3
5
When the waveform output select bits are set to “11” (bit 1
= bit 0 = “1”), RTP13 to RTP10 and RTP03 to RTP00
become pulse output port pins.
When the waveform output
When the waveform output select bits are set to “11” (bit 1
= bit 0 = “1”), pulse output port pins are divided into two
groups; one consists of RTP13 to RTP10, RTP03, RTP02
and the other consists of RTP01 and RTP00.
When the waveform output
Page 90,
Fig. 92,
address 7016
0 00
?
A-D interrupt control register
(7016)
00 0
?
A-D conversion interrupt control register (7016)
Page 89,
Fig. 93,
address 8116
00 0
0
CS0 control register H
(8116)
0
000
0
CS0 control register H
(8116)
1
Page 91,
Left column,
Line 17
from pin XIN and output a multiplied clock.
5
from pin XIN and generates a multiplied clock.
Page 91,
Left column,
Lines 11, 12
5
, the oscillation circuit stops it’s operation and resu-
mes the current dissipation.
, the oscillation circuit stops it’s operation, and the
current dissipation is reduced.
Page 92,
Right column,
Lines 4 to 5
In this selection, be sure that multiplied f(XIN) does
not exceed 26 MHz.
The PLL multiplication ratio must be set so that the
frequency of the PLL output clock (fPLL) must be in the
range from 10 MHz to 26 MHz.
Page 92,
Right column,
Lines 10 to 11
the PLL output clock (fPLL). (In other words, set bit 5
to “1”.)
the PLL output clock (fPLL). (In other words, set bit 5
to “1”.) Note that, after reset, the PLL multiplication ratio
select bits are allowed to be changed only once.
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