參數(shù)資料
型號： M37902FCCHP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 26 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù)： 115/143頁
文件大?。?/td> 1148K
代理商： M37902FCCHP
73
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
________
Once transmission has started, the TEi flag, TIi flag, and CTSi signal
are ignored until data transmission is completed.
Therefore, transmission does not stop until it completes event if, dur-
ing transmission, the TEi flag is cleared to “0” or CTSi input is set to
“1”.
The transmission start condition indicated by TEi flag, TIi flag, and
________
CTSi is checked while the TENDi signal shown in Figure 73 is “H”.
Therefore, data can be transmitted continuously if the next transmis-
sion data is written in the transmit buffer register and TIi flag is
cleared to “0” before the TENDi signal goes “H”.
Bit 3 (TXEPTYi flag) of UARTi transmit/receive control register 0
changes to “1” at the next cycle just after the TENDi signal goes “H”
and changes to “0” when transmission starts. Therefore, this flag can
be used to determine whether data transmission is completed.
When the TIi flag changes from “0” to “1”, the interrupt request bit of
the UARTi transmit interrupt control register is set to “1”.
Transmission
Transmission is started when bit 0 (TEi flag transmit enable flag) of
UARTi transmit/receive control register 1 is “1”, bit 1 (TIi flag) is “0”,
________
and CTSi input (in other words, transmit enable signal input from re-
ceiver) is “L.” The TIi flag indicates whether the transmit buffer is
empty or not. It is cleared to “0” when data is written in the transmit
buffer; it is set to “1” when the contents of the transmit buffer register
is transferred to the transmit register.
When all of the transmission conditions are satisfied, transmit data
is transferred to the transmit register, and transmit operation starts.
As shown in Figures 73 and 74, data is output from the TXDi pin with
the stop bit or parity bit specified by bits 4 to 6 of UARTi transmit/re-
ceive mode register. The data is output from the least significant bit.
When the transmit register becomes empty after the contents has
been transmitted, data is transferred automatically from the transmit
buffer register to the transmit register if the next transmit start condi-
tion is satisfied. Then, the next transmission is performed
succeedingly.
Fig. 75 Receive timing example when 8-bit asynchronous communication with no parity and 1 stop bit selected
Start bit
Stop bit
Start bit
D0
D1
D7
Check to be “L” level
Starting at the falling
edge of start bit
Data fetched
fi or fEXT
REi
RXDi
Receive
clock
RIi
RTSi
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