參數(shù)資料
型號: M37735S4LHP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, 12 MHz, MICROCONTROLLER, PQFP80
封裝: 12 X 12 MM, 0.50 MM PITCH, FINE PITCH, PLASTIC, LQFP-80
文件頁數(shù): 6/37頁
文件大?。?/td> 819K
代理商: M37735S4LHP
13
MITSUBISHI MICROCOMPUTERS
M37735S4LHP
16-BIT CMOS MICROCOMPUTER
New
product
___
CS0
to CS4 are the chip select signals and are “L” when the address
____
shown in Table 2 is accessed. RSMP is the ready-sampling signal
___
which is output for the RDY input described later when the external
____
memory area is accessed. By inputting logical AND of RSMP and
___
____
CSn
(n = 0 to 4) to the RDY pin, read/write term for any address areas
can be extended by 1 cycle of clock
1
. In addition, the read/write
term can also be extended by 2 cycles of clock
1
if the above
function and wait 0/1 function specified with the wait bit are used
together.
Pins P10/A8/D8 — P17/A15/D15 have two functions depending on the
level of the BYTE pin.
When the BYTE pin level is “L”, pins P10/A8/D8 — P17/A15/D15 function
___
as address (A8 to A15) output pins while RDE or WEL, WEH are “H”
and as odd address data I/O pins while these signals are “L”. However,
___
if an internal memory is read, external data is ignored while RDE is
“L”.
When the BYTE pin level is “H”, pins P10/A8/D8 — P17/A15/D15 function
as address (A8 to A15) output pins.
Pins P20/A0/D0 — P27/A7/D7 have two functions depending on the
level of the BYTE pin.
When the BYTE pin level is “L”, pins P20/A0/D0 — P27/A7/D7 function
___
as address (A0 to A7) output pins while RDE or WEL, WEH are “H” and
as even address data I/O pins while these signals are “L”. However,
___
if an internal memory is read, external data is ignored while RDE is
“L”.
When the BYTE pin level is “H”, pins P20/A0/D0 — P27/A7/D7 function
___
as address (A0 to A7) output pins while RDE or WEL, WEH are “H” and
as even and odd address data I/O pins while these signals are “L”.
However, if an internal memory is read, external data is ignored while
___
RDE
is “L”.
___
WEL
, WEH are the write-enable low signal and the write-enable high
signal, respectively. These signals are “L” during the data write term
of the write cycle, but their operations differ depending on the BYTE
pin level.
___
In the case the BYTE pin level is “L”, WEL is “L” when writing to
___
an even address, WEH is “L” when writing to an odd address, and
___
both WEL and WEH are “L” when writing to even and odd addresses.
In the case the BYTE pin level is “H”, regardless of address, only
___
WEL
is “L”, and WEH retains “H”. WEL and WEH can also be fixed to
___
“H” when the internal memory is accessed, same as RDE, by writing
“1” to the signal output disable selection bit.
ALE is an address latch enable signal used to latch the address signal
from a multiplexed signal of address and data. The latch is transparent
while ALE is “H” to let the address signal pass through and held
while ALE is “L”.
____
HLDA
is a hold acknowledge signal and is used to notify externally
____
when the microcomputer receives HOLD input and enters into hold
state.
____
HOLD
is a hold request signal. It is an input signal used to put the
____
microcomputer in hold state. HOLD input is accepted when the internal
clock
falls from “H” level to “L” level while the bus is not used.
___
____
___
Pins P00/CS0 P31/WEH and RDE are floating while the microcomputer
____
stays in hold state. After HLDA signal changes to “L” level and one
cycle of internal clock
passed, these ports become floating. After
____
HLDA
signal changes to “H” level and one cycle of internal clock
passed, these ports are released from floating state.
___
RDY
is a ready signal. If this signal goes “L”, the internal clock
___
stops at “L”. RDY is used when slow external memory is attached.
P42/
1
pin is an output pin for clock
1
. The
1
output is
___
independent of RDY and does not stop even when internal clock
___
stops because of “L” input to the RDY pin.
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