參數(shù)資料
型號： M37735S4LHP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MICROCONTROLLER, PQFP80
封裝： FINE PITCH, PLASTIC, QFP-80
文件頁數(shù)： 38/63頁
文件大?。?/td> 8367K
代理商： M37735S4LHP
CENTRAL PROCESSING UNIT (CPU)
7733 Group User’s Manual
2–5
2.1.5 Program counter (PC)
The program counter consists of 16 bits. This counter indicates the low-order 16 bits of a store address,
which consists of 24 bits, of an instruction to be executed next, in other words an instruction which is read
from an instruction queue buffer.
At reset, value “FF16” is set to the high-order byte (PCH) of the program counter and value “FE16” is set
to the low-order byte (PCL) of the counter. And then, immediately after reset, the contents of the reset’s
vector addresses (addresses FFFE16, FFFF16) are set to the counter.
Figure 2.1.3 shows the program counter and the program bank register.
Fig. 2.1.3 Program counter and program bank register
2.1.6 Program bank register (PG)
The program bank register consists of 8 bits. (Refer to Figure 2.1.3.) This register indicates the high-order
8 bits of a store address, which consists of 24 bits, of an instruction to be executed next, in other words
an instruction which is read from an instruction queue buffer. These 8 bits indicate “bank.” The contents
of the program bank register is automatically incremented by 1 when a carry occurs in the following cases:
When a certain value is added to the contents of the program counter
When the displacement is added to the program counter by executing a branch instruction and others
The contents of the program bank register is automatically decremented by 1 when a borrow occurs in the
following case:
When a certain value is subtracted from the contents of the program counter
Therefore, when normally programming, it is not necessary to give consideration to bank boundaries.
At reset, this register is cleared to “0016.”
PCH
PCL
b7
b0 b15
b8 b7
b0
(b16)
PG
(b23)
2.1 Central processing unit
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