參數資料
型號: M37702M2A-278FP
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
中文描述: 單片16位CMOS微機
文件頁數: 14/59頁
文件大小: 811K
代理商: M37702M2A-278FP
14
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt types
DBC
Watchdog timer
Zero divide
BRK instruction
Setting value
0
7
7
Not change value of IPL.
Not change value of IPL.
Table 3. Value set in processor interrupt level (IPL) during an
interrupt
As shown in Figure 9, there are three different interrupt priority
resolution time from which one is selected by software. After the
selected time has elapsed, the highest priority is determined and
is processed after the currently executing instruction has been
completed.
The time is selected with bits 4 and 5 of the processor mode reg-
ister (address 5E
16
) shown in Figure 10. Table 4 shows the
relationship between these bits and the number of cycles. After a
reset, the processor mode register is initialized to “00
16
” and
therefore, the longest time is selected.
However, the shortest time should be selected by software.
Priority level resolution time selection bit
Bit 5
0
0
1
φ
: internal clock
Table 4. Relationship between priority level resolution time
selection bit and number of cycles
Bit 4
0
1
0
Number of cycles
7 cycles of
φ
4 cycles of
φ
2 cycles of
φ
Fig. 10 Processor mode register configuration
Fig. 9 Interrupt priority resolution time
0
1
2
Internal clock
φ
Operation code fetch cycle
Sampling pulse
Priority resolution time
Select from 0 to 2 with bits
4 and 5 of the processor
mode register
7
Processor mode register (5E
16
)
6
5
4
3
2
1
0
Processor mode bits
0 0 : Single-chip mode
0 1 : Memory expansion mode
1 0 : Microprocessor mode
1 1 : Evaluation chip mode
Wait bit
0 : Wait
1 : No wait
Software reset bit
The processor is reset when this bit is set to “1”
.
Priority resolution time selection bits
0 0 : Select 0 in Figure 9
0 1 : Select 1 in Figure 9
1 0 : Select 2 in Figure 9
Test mode bit
Must be “0”
Clock
φ
1
output selection bit
0 : No
φ
1
output
1 :
φ
1
output
0
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