參數(shù)資料
型號(hào)： M37702M2A-278FP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
中文描述： 單片16位CMOS微機(jī)
文件頁(yè)數(shù)： 12/59頁(yè)
文件大?。?/td> 811K
代理商： M37702M2A-278FP
12
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
INTERRUPTS
Table 1 shows the interrupt types and the corresponding interrupt
vector addresses. Reset is also treated as a type of interrupt and
is discussed in this section, too. DBC is an interrupt used during
debugging.
Interrupts other than reset, DBC, watchdog timer, zero divide, and
BRK instruction all have interrupt control registers. Table 2 shows
the addresses of the interrupt control registers and Figure 6 shows
the bit configuration of the interrupt control register.
Use the SEB and CLB instructions when setting each interrupt
control register.
The interrupt request bit is automatically cleared by the hardware
during reset or when processing an interrupt.
Also, interrupt request bits other than DBC and watchdog timer
INT
2
to INT
0
are external interrupts and whether to cause an inter-
rupt at the input level (level sense) or at the edge (edge sense)
can be selected with the level sense/edge sense selection bit. Fur-
thermore, the polarity of the interrupt input can be selected with
polarity selection bit.
Timer and UART interrupts are described in the respective sec-
tion. The priority of interrupts when multiple interrupts are caused
simultaneously is partially fixed by hardware, but, it can also be
adjusted by software as shown in Figure 7. The hardware priority
is fixed the following:
reset > DBC > watchdog timer > other interrupts
Interrupts
A-D conversion
UART1 transmit
UART1 receive
UART0 transmit
UART0 receive
Timer B2
Timer B1
Timer B0
Timer A4
Timer A3
Timer A2
Timer A1
Timer A0
INT
2
external interrupt
INT
1
external interrupt
INT
0
external interrupt
DBC (unusable)
Break instruction
Zero divide
Reset
Vector addresses
00FFD6
16
00FFD8
16
00FFDA
16
00FFDC
16
00FFDE
16
00FFE0
16
00FFE2
16
00FFE4
16
00FFE6
16
00FFE8
16
00FFEA
16
00FFEC
16
00FFEE
16
00FFF0
16
00FFF2
16
00FFF4
16
00FFF6
16
00FFF8
16
00FFFA
16
00FFFC
16
00FFFE
16
00FFD7
16
00FFD9
16
00FFDB
16
00FFDD
16
00FFDF
16
00FFE1
16
00FFE3
16
00FFE5
16
00FFE7
16
00FFE9
16
00FFEB
16
00FFED
16
00FFEF
16
00FFF1
16
00FFF3
16
00FFF5
16
00FFF7
16
00FFF9
16
00FFFB
16
00FFFD
16
00FFFF
16
Table 1. Interrupt types and the interrupt vector addresses
Fig. 6 Interrupt control register configuration
7
Interrupt priority
Interrupt request bit
0 : No interrupt
1 : Interrupt
6 5 4 3 2 1 0
Interrupt control register configuration for A-D converter, UART0, UART1, timer A0 to timer A4, and
timer B0 to timer B2
7
Interrupt priority
Interrupt request bit
0 : No interrupt
1 : Interrupt
Polarity selection bit
0 : Set interrupt request bit at “H” level for level sense and when changing
from “H” to “L” level for edge sense.
1 : Set interrupt request bit at “L” level for level sense and when changing
from “L” to “H” level for edge sense.
Level sense/edge sense selection bit
0 : Edge sense
1 : Level sense
6 5 4 3 2 1 0
Interrupt control register configuration for
INT
2
to
INT
0.
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