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參數(shù)資料
| 型號(hào)： | M37641M8 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁(yè)數(shù)： | 14/149頁(yè) |
| 文件大?。?/td> | 1997K |
| 代理商： | M37641M8 |
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14
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7641 Group
PRELIMINARY
Notice: This is not a final specification.
change.
Some parametric limits are subject to
I/O PORTS
Direction Registers
The I/O ports P0–P8 have direction registers which determine the
input/output direction of each individual pin. Each bit in a direction
register corresponds to one pin, each pin can be set to be input port
or output port.
When “0” is written to the bit corresponding to a pin, that pin be-
comes an input pin. When “1” is written to that bit, that pin becomes
an output pin.
If data is read from a pin set to output, the value of the port output
latch is read, not the value of the pin itself. Pins set to input are float-
ing. If a pin set to input is written to, only the port output latch is
written to and the pin remains floating.
Slew Rate Control
By setting bits 0 to 5 of the port control register (address 0010
16
) to
“1”, slew rate control is enabled. VIHL or CMOS level can be used as
a port P2 input level; CMOS or TTL level can be used as an input
level of master CPU bus interface.
Pull-up Control
By setting the port P2 pull-up control register (address 0012
16
), pull-
up of each pin of port P2 can be controlled with a program.
However, the contents of port P2 pull-up control register do not affect
ports programmed as the output ports but as the input ports.
Fig. 11 Structure of port control and port P2 pull-up control
registers
Port control register (address 0010
16
)
PTC
Port P0 to P3 slew rate control bit (
Note 1
)
0: Disabled
1: Enabled
Port P4 slew rate control bit (
Note 1
)
0: Disabled
1: Enabled
Port P5 slew rate control bit (
Note 1
)
0: Disabled
1: Enabled
Port P6 slew rate control bit (
Note 1
)
0: Disabled
1: Enabled
Port P7 slew rate control bit (
Note 1
)
0: Disabled
1: Enabled
Port P8 slew rate control bit (
Note 1
)
0: Disabled
1: Enabled
Port P2 input level select bit
0: Reduced VIHL level input (
Note 2
)
1: CMOS level input
Master CPU bus input level select bit
0: CMOS level input
1: TTLlevel input
Notes 1
: The slew rate function can reduce di/dt by modifying an internal
buffer structure.
2
: The characteristics of VIHL level is basically the same as that of
TTL level. But, its switching center point is a little higher than
TTL
’
s. Refer to section
“
Recommended operating conditions
”
.
b0
b7
Port P2 pull-up control register
(address 0012
16
) PUP2
b0
b7
Port P2
0
pull-up control bit
0: Disabled
1: Enabled
Port P2
1
pull-up control bit
0: Disabled
1: Enabled
Port P2
2
pull-up control bit
0: Disabled
1: Enabled
Port P2
3
pull-up control bit
0: Disabled
1: Enabled
Port P2
4
pull-up control bit
0: Disabled
1: Enabled
Port P2
5
pull-up control bit
0: Disabled
1: Enabled
Port P2
6
pull-up control bit
0: Disabled
1: Enabled
Port P2
7
pull-up control bit
0: Disabled
1: Enabled
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