參數(shù)資料
型號： M37641M8
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁數(shù)： 108/149頁
文件大小： 1997K
代理商： M37641M8
108
7641 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
change.
Some parametric limits are subject to
G
Erase All Blocks Command (20
16
/20
16
)
By writing the command code
“
20
16
”
in the first bus cycle and the
confirmation command code
“
20
16
”
in the second bus cycle that
follows, the operation of erase all blocks (erase and erase verify)
starts.
Whether the erase all blocks command is terminated can be con-
firmed by reading the status register or the RY/BY Status Flag of
flash memory control register. When the erase all blocks operation
starts, the read status register mode is entered automatically and
the contents of the status register can be read out at the data bus
(DB
0
to DB
7
). The status register bit 7 (SR7) is set to
“
0
”
at the
same time the erase operation starts and is returned to
“
1
”
upon
completion of the erase operation. In this case, the read status
register mode remains active until another command is written.
The RY/BY Status Flag is
“
0
”
during erase operation and
“
1
”
when
the erase operation is completed as is the status register bit 7.
After the erase all blocks end, erase results can be checked by
reading the status register. For details, refer to the section where
the status register is detailed.
G
Block Erase Command (20
16
/D0
16
)
By writing the command code
“
20
16
”
in the first bus cycle and the
confirmation command code
“
D0
16
”
and the blobk address in the
second bus cycle that follows, the block erase (erase and erase
verify) operation starts for the block address of the flash memory
to be specified.
Whether the block erase operation is completed can be confirmed
by reading the status register or the RY/BY Status Flag of flash
memory control register. At the same time the block erase opera-
tion starts, the read status register mode is automatically entered,
so that the contents of the status register can be read out. The
status register bit 7 (SR7) is set to
“
0
”
at the same time the block
erase operation starts and is returned to
“
1
”
upon completion of
the block erase operation. In this case, the read status register
mode remains active until the read array command (FF
16
) is writ-
ten.
The RY/BY Status Flag is
“
0
”
during block erase operation and
“
1
”
when the block erase operation is completed as is the status reg-
ister bit 7.
After the block erase ends, erase results can be checked by read-
ing the status register. For details, refer to the section where the
status register is detailed.
W
r
i
t
e
2
0
1
6
2
o
0
1
c
k
6
/
a
D
d
0
1
d
6
e
B
l
r
s
s
E
r
a
s
e
c
o
m
p
l
e
t
e
d
N
O
Y
E
S
Start
Write
SR5 = 0
E
r
a
s
e
e
r
r
o
r
YES
N
O
2
D
0
1
0
1
6
:
6
:
E
B
r
l
a
o
s
c
e
k
a
e
l
r
l
a
b
s
l
o
e
c
k
s
SR7 = 1
or
RY/BY = 1
S
t
a
t
u
s
r
e
a
r
e
d
g
i
s
t
e
r
Fig. 92 Erase flowchart
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