69
7641 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
change.
Some parametric limits are subject to
X : Not fixed
Notes 1:
When using the endpoint 1, this contents are “01
16
”.
2:
Since the initial values for other than above mentioned registers and RAM contents are indefinite at reset, they must be set.
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(28)
(29)
(30)
(31)
(32)
(33)
(34)
(35)
(36)
(37)
(38)
(39)
(40)
(41)
(42)
(43)
(44)
(45)
(46)
(47)
(48)
(49)
(50)
(51)
(52)
(53)
(54)
(55)
(56)
(57)
(58)
(59)
(60)
(61)
(62)
(63)
(64)
(65)
(66)
(67)
(68)
(69)
(70)
(71)
(72)
(73)
(74)
(75)
(76)
(77)
(78)
(79)
(80)
(81)
(82)
(83)
(84)
(85)
(86)
(87)
(88)
(89)
(90)
(91)
(92)
(93)
Register contents
0032
16
0033
16
0036
16
0038
16
003A
16
003B
16
003E
16
003F
16
0040
16
0041
16
0042
16
0043
16
0044
16
0045
16
0046
16
0047
16
0048
16
0049
16
004A
16
004C
16
004D
16
004E
16
0050
16
0051
16
0052
16
0053
16
0054
16
0055
16
0056
16
0057
16
0058
16
0059
16
005A
16
005B
16
005C
16
005D
16
005E
16
005F
16
006A
16
006C
16
006D
16
006E
16
006F
16
FFC916
(PS)
(PC
H
)
(PC
L
)
Address
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
FF
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
FF
16
FF
16
FF
16
FF
16
Address Register contents
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
FF
16
FF
16
FF
16
FF
16
FF
16
FF
16
00
16
00
16
00
16
FF
16
FF
16
00
16
00
16
FFFB
16
contents
FFFA
16
contents
CPU mode register A (CPUA)
CPU mode register B (CPUB)
Interrupt request register A (IREQA)
Interrupt request register B (IREQB)
Interrupt request register C (IREQC)
Interrupt control register A (ICONA)
Interrupt control register B (ICONB)
Interrupt control register C (ICONC)
Port P0 (P0)
Port P0 direction register (P0D)
Port P1 (P1)
Port P1 direction register (P1D)
Port P2 (P2)
Port P2 direction register (P2D)
Port P3 (P3)
Port P3 direction register (P3D)
Port control register (PTC)
Interrupt polarity select register (IPOL)
Port P2 pull-up control register (PUP2)
USB control register (USBC)
Port P6 (P6)
Port P6 direction register (P6D)
Port P5 (P5)
Port P5 direction register (P5D)
Port P4 (P4)
Port P4 direction register (P4D)
Port P7 (P7)
Port P7 direction register (P7D)
Port P8 (P8)
Port P8 direction register (P8D)
Clock control register (CCR)
Timer XL (TXL)
Timer XH (TXH)
Timer YL (TYL)
Timer YH (TYH)
Timer 1 (T1)
Timer 2 (T2)
Timer 3 (T3)
Timer X mode register (TXM)
Timer Y mode register (TYM)
Timer 123 mode register (T123M)
Serial I/O control register 1 (SIOCON1)
Serial I/O control register 2 (SIOCON2)
Special count source generator 1 (SCSG1)
Special count source generator 2 (SCSG2)
Special count source mode register
(SCSGM)
UART1 mode register (U1MOD)
0000
16
0001
16
0002
16
0003
16
0004
16
0005
16
0006
16
0007
16
0008
16
0009
16
000A
16
000B
16
000C
16
000D
16
000E
16
000F
16
0010
16
0011
16
0012
16
0013
16
0014
16
0015
16
0016
16
0017
16
0018
16
0019
16
001A
16
001B
16
001C
16
001D
16
001F
16
0020
16
0021
16
0022
16
0023
16
0024
16
0025
16
0026
16
0027
16
0028
16
0029
16
002B
16
002C
16
002D
16
002E
16
002F
16
0030
16
1
0 0 0 0 0
0
UART1 status register (U1STS)
UART1 control register (U1CON)
UART1 RTS control register (U1RTSC)
UART2 mode register (U2MOD)
UART2 status register (U2STS)
UART2 control register (U2CON)
UART2 RTS control register (U2RTSC)
DMAC index and status register
(DMAIS)
DMAC channel x mode register 1 (DMAx1)
DMAC channel x mode register 2 (DMAx2)
DMAC channel x source register Low (DMAxSL)
DMAC channel x source register High (DMAxSH)
DMAC channel x destination register Low (DMAxDL)
DMAC channel x destination register
High
(DMAxDH)
DMAC channel x transfer count register Low (DMAxCL)
DMAC channel x transfer count register High (DMAxCH)
Data bus buffer register 0 (DBB0)
Data bus buffer status register 0 (DBBS0)
Data bus buffer control register 0 (DBBC0)
Data bus buffer register 1 (DBB1)
Data bus buffer status register 1 (DBBS1)
Data bus buffer control register 1 (DBBC1)
USB address register (USBA)
USB power management register (USBPM)
USB interrupt status register 1 (USBIS1)
USB interrupt status register 2 (USBIS2)
USB interrupt enable register 1 (USBIE1)
USB interrupt enable register 2 (USBIE2)
USB frame number register Low (USBSOFL)
USB frame number register High (USBSOFH)
USB endpoint index register (USBINDEX)
USB endpoint x IN control register (IN_CSR)
USB endpoint x OUT control register (OUT_CSR)
USB endpoint x IN max. packet size register (IN_MAXP)
USB endpoint x OUT max. packet size register (OUT_MAXP)
USB endpoint x OUT write count register Low (WRT_CNTL)
USB endpoint x OUT write count register High (WRT_CNTH)
USB endpoint FIFO mode register (USBFIFOMR)
Flash memory control register (FMCR)
Frequency synthesizer control register (FSC)
Frequency synthesizer multiply register 1 (FSM1)
Frequency synthesizer multiply register 2 (FSM2)
Frequency synthesizer divide register (FSM2)
ROM code protect control register (ROMCP)
Processor status register
Program counter
0 0
0 0
1 1
0 0
0
1 1
0 0
1
0 0
0
0
0
0 0
1
1
1 0 0 0 0 0 0 0
1
0 0 0 0 0
0
1
1 0 0 0 0 0 0 0
1
0 1 1 0 0
0
1
0
1 0
0
0 0
0
0
0
1 0
0
0 0
0
0
0 0 0 0 0
0
1
0
0 0 0
0
1
0
1
0
1
0 0
0
0
0
0
0
1
0 0
0
0
0
0
0 1
0
1
(Note 1)
(Note 1)
(Note 3)
(Note 3)
3
: The flash memory control register and the ROM code protect control register exists in the flash memory version only.
Fig. 63 Internal status at reset