參數(shù)資料
型號(hào)： M37641F8HP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁(yè)數(shù)： 116/149頁(yè)
文件大?。?/td> 1997K
代理商： M37641F8HP
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116
7641 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
change.
Some parametric limits are subject to
DB
0
to DB
7
Data output
Status register data output
High impedance
High impedance
Command/data input
Command input
Command input
High impedance
RP
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IL
WE
V
IH
V
IH
V
IH
X
V
IL
V
IL
V
IL
X
OE
V
IL
V
IL
V
IH
X
V
IH
V
IH
V
IH
X
CE
V
IL
V
IL
V
IL
V
IH
V
IL
V
IL
V
IL
X
Pin name
Mode
Array
Status register
Output disabled
Stand by
Program
Erase all blocks
Block erase
Write
Deep power down
Read
Note
: X can be V
IL
or V
IH
.
Table 29 Relationship between control signals and bus operation modes
Address
The User ROM has some blocks as shown in Figure 98. The block
address is the maximum address value of each block.
User ROM and Boot ROM Areas
In parallel I/O mode, the User ROM and Boot ROM areas shown
in Figure 98 can be rewritten. The BSEL pin is used to choose be-
tween these two areas. The User ROM area is selected by pulling
the BSEL input low; the Boot ROM area is selected by driving the
BSEL input high. Both areas of flash memory can be operated on
in the same way.
Program and block erase operations can be performed only in the
User ROM area.
The User ROM area is 32 Kbytes in size. In parallel I/O mode, it is
located at addresses 8000
16
through FFFF
16
. The Boot ROM area
is 4 Kbytes in size. In parallel I/O mode, it is located at addresses
F000
16
through FFFF
16
. Make sure program and block erase op-
erations are always performed within this address range. (Access
to any location outside this address range is prohibited.)
In the Boot ROM area, an erase block operation is applied to only
one 4 Kbyte block. The boot ROM area has had a standard serial
I/O mode control program stored in it when shipped from the
Mitsubishi factory. Therefore, using the MCU in standard serial I/O
mode, do not rewrite to the Boot ROM area.
Outline Performance (Parallel I/O Mode)
In parallel I/O mode, bus operation modes
—
Read, Output Dis-
able, Standby, Write, and Deep Power Down
—
are selected by
the state of the CE, OE, WE, and RP input pins.
The contents of erase, program, and other operations are selected
by writing a software command. The data, status register, etc. in a
memory can only be read out by a read after software command
input.
Program and erase operations are controlled using software com-
mands.
The following explains about bus operation modes, software com-
mands, and status register.
E000
16
FFFF
16
User ROM area
4 Kbyte
Boot ROM area
Notes 1
: The Boot ROM area can be rewritten in only parallel input/output mode. (Access to
any other areas is inhibited.)
2
: To specify a block, use the maximum address in the block.
Parallel I/O mode
BSEL = 0
BSEL = 1
C000
16
Block 1 : 8 Kbytes
Block 2 : 16 Kbytes
Block 0 : 8 Kbytes
8000
16
F000
16
FFFF
16
Fig. 98 Internal flash memory block diagram
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