25
7641 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
change.
Some parametric limits are subject to
Fig. 20 Structure of timer X mode register
Timer X
Timer X is a 16-bit timer that can be selected in one of four modes.
The timer X
’
s internal clock and count source can be selected and
a write control is possible by using the timer X mode register.
In all modes the count operation can halt by setting the Timer X
Count Stop Bit to
“
1
”
. Additionally, each timer underflow sets the
Interrupt Request Bit to
“
1
”
.
(1) Timer Mode
The timer counts the SCSGCLK (Special Count Source Genera-
tor) or one of the internal clock
φ
divided by 8, 16, 32, 64.
(2) Pulse Output Mode
Each time the timer underflows, a signal output from the CNTR
0
pin is inverted. Except for this, the operation in pulse output mode
is the same as in timer mode.
When the CNTR
0
Active Edge Switch Bit is
“
0
”
, the CNTR
0
pin
starts pulses output beginning at
“
H
”
; when this bit is
“
1
”
, the
CNTR
0
pin starts pulses output beginning at
“
L
”
.
When using a timer in this mode, set the port P4
3
direction regis-
ter to output mode.
(3) Event Counter Mode
The timer counts signals input through the CNTR
0
pin.
Except for this, the operation in event counter mode is the same
as in timer mode.
When the CNTR
0
Active Edge Switch Bit is
“
0
”
, the rising edge is
counted; when this bit is
“
1
”
, the falling edge is counted.
When using a timer in this mode, set the port P4
3
direction regis-
ter to input mode.
(4) Pulse Width Measurement Mode
When the CNTR
0
Active Edge Switch Bit is
“
0
”
, the timer counts
while the input signal of CNTR
0
pin is at
“
H
”
; when it is
“
1
”
, the
timer counts while the input signal of CNTR
0
pin is at
“
L
”
.
The timer counts the SCSGCLK or one of the internal clock
φ
di-
vided by 8, 16, 32, 64 as its count source.
When using a timer in this mode, set the port P4
3
direction regis-
ter to input mode.
I
Notes
G
Timer X Write Control
If the Timer X Write Control Bit is
“
1
”
, when the value is written in
the address of timer X, the value is loaded only in the latch. The
value in the latch is loaded in timer X after timer X underflows.
If the Timer X Write Control Bit is
“
0
”
, when the value is written in
the address of timer X, the value is loaded in the timer X and the
latch at the same time.
When the value is to be written in latch only, unexpected value
may be set in the high-order timer if the writing in high-order latch
and the underflow of timer X are performed at the same timing.
G
CNTR
0
Interrupt Active Edge Selection
The CNTR
0
interrupt active edge depends on the selection of
CNTR
0
Active Edge Switch Bit.
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