參數(shù)資料
型號(hào)： M37640E8FS
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 24 MHz, MICROCONTROLLER, PQFP80
封裝： 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80
文件頁(yè)數(shù)： 28/97頁(yè)
文件大?。?/td> 1885K
代理商： M37640E8FS
33
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.17.2 Timer Y
Timer Y is a 16-bit timer that has a 16-bit reload latch,
and can be placed in any of four modes by setting
TYM4 and TYM5 (bits 4 and 5) (see Figure 1.34). The
desired mode is selected by modifying the values of
TYM4 and TYM5.
1.17.2.1 Read and Write Method
Read and write operations on the high and low-order
bytes of Timer Y must be performed in a specific or-
der.
Write Method
When writing to the timer, the lower order byte is
written first. This data is placed in a temporary reg-
ister that is assigned the same address as Timer
YL. Next, the high-order byte is written. Then, the
data is placed in the Timer YH reload latch and the
low-order byte is transferred from its temporary reg-
ister to the Timer YL reload latch. At this point, if the
Timer Y Data Write Control Bit (TYM0) (bit 0) is low,
the value in the Timer Y reload latch is also loaded
in Timer Y. If TYM0 is “1”, the data in the Timer Y
reload latch is loaded in Timer Y after Timer Y
underflows.
Fig. 1.34. Timer Y Mode Register (TYM)
Read Method
When reading Timer Y, the high-order byte is read
first. Reading the high-order byte causes the values
of Timer YH and Timer YL to be placed in temporary
registers that are assigned the same addresses as
Timer YH and Timer YL. The low-order byte of
Timer Y is then read from its temporary register.
This operation assures the correct reading of Timer
Y while it is counting.
1.17.2.2 Count Stop Control
If the Timer Y Count Stop Bit (TYM7) (bit 7) is set to a
“1”, Timer Y stops counting in all four modes.
Timer Mode
Count Source:
F/n (where n is 8, 16, 32, or 64)
In this mode, each time the timer underflows, the
corresponding timer interrupt request bit is set to a
“1”, the contents of the timer latch are loaded into
the timer, and the count down sequence begins
again.
In Timer mode, the signal TYOUT can also be
brought out on the CNTR1 pin. This is controlled by
TYM1 (bit1).
TYM0
Timer Y Data Write Control Bit (bit 0)
0 : Write data in latch and timer
1 : Write data in latch only
TYM1
Timer Y Output Control Bit (bit 1)
0 : TYOUT output disable
1 : TYOUT output enable
TYM3,2
Timer Y Frequency Division Ratio Bits (bit 3,2)
Bit 2
Bit 1
00 :
. divided by 8
01 :
. divided by 16
10 :
. divided by 32
11 :
. divided by 64
TYM5,4
Timer Y Mode Bits (bits 5,4)
Bit 2
Bit 1
0
0 : Timer Mode
0
1 : Pulse period measurement mode
1
0 : Event counter mode
1
1 : HL pulse width measurement mode (continu-
ously measures high period and low period)
TYM6
CNTR1 Polarity Select Bit (bit 6)
0 : For event counter mode, clocked by rising edge
For pulse period measurement mode, falling edge detection
For CNTR1 interrupt request, falling edge active
For TYOUT, start on high output
1 : For event counter mode, clocked on falling edge
For pulse period measurement mode, rising edge detection
For CNTR1 interrupt request, rising edge active
For TYOUT, start on low output
TYM7
Timer Y Stop Bit (bit 7)
0 : Count start
1 : Count stop
TYM7
TYM5
TYM4
TYM3
TYM2
TYM1
TYM0
MSB
7
LSB
0
Address: 0028
16
Access: R/W
Reset: 00
16
TYM6
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