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參數(shù)資料
| 型號： | M37640E8FS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 24 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80 |
| 文件頁數(shù)： | 22/97頁 |
| 文件大?。?/td> | 1885K |
| 代理商： | M37640E8FS |
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28
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 1.30. Interrupt Polarity Register (IPOL)
Fig. 1.29. Interrupt Control Register C (ICONC)
Fig. 1.28. Interrupt Control Register B (ICONB)
Fig. 1.27 Interrupt Control Register A (ICONA)
ICA5
ICA4
ICA2
ICA1
ICA0
MSB
LSB
0
ICA3
ICA7
ICA6
ICA 0
USB Function Interrupt Enable (bit 0)
ICA 1
USB SOF Interrupt Enable (bit 1)
ICA 2
External Interrupt 0 Enable (bit 2)
ICA 3
External Interrupt 1 Enable (bit 3)
ICA 4
DMAC channel 0 Interrupt Enable (bit 4)
ICA 5
DMAC channel 1 Interrupt Enable (bit 5)
ICA 6
UART1 Receive Buffer Full Interrupt Enable (bit 6)
ICA 7
UART1 Transmit Interrupt Enable (bit 7)
0: Interrupt Disable
1: Interrupt Enable
Address: 0005
16
Access:
R/W
Reset:
00
16
The interrupt polarity register allows the user to se-
lect the edge that will trigger an external interrupt
Reserved
INT1 Pol INT0 Pol
MSB
7
LSB
0
Reserved
Address: 0011
16
Access:
R/W
Reset:
00
16
INT0 Pol
INT0 Interrupt Edge Selection Bit
0: Falling edge selected
1: Rising edge selected
INT1 Pol
INT1 Interrupt Edge Selection Bit
0: Falling edge selected
1: Rising edge selected
Bits 2-7
Reserved (Read/Write “0”)
request. The polarity register (IPOL) for the external
interrupts is shown in Figure 1.30.
ICC 0
Timer 3 Interrupt Enable (bit 0)
ICC 1
External CNTR0 Interrupt Enable (bit 1)
ICC 2
External CNTR1 Interrupt Enable (bit 2)
ICC 3
SIO Interrupt Enable (bit 3)
ICC 4
Input Buffer Full Interrupt Enable (bit 4)
ICC 5
Output Buffer Empty Interrupt Enable (bit 5)
ICC 6
Key-on Wake up Interrupt Enable (bit 6)
0: Interrupt Disable
1: Interrupt Enable
ICC 7
Reserved (Read/Write “0”)
Address: 0007
16
Access:
R/W
Reset:
00
16
ICC5
ICC4
ICC2
ICC1
ICC0
MSB
7
LSB
0
ICC3
ICC6
Reserved
ICB5
ICB4
ICB2
ICB1
ICB0
MSB
7
LSB
0
ICB3
ICB7
ICB6
ICB 0
UART1 Error Sum Interrupt Enable (bit 0)
ICB 1
UART2 Receive Buffer Full Interrupt Enable (bit 1)
ICB 2
UART2 Transmit Interrupt Enable (bit 2)
ICB 3
UART2 Error Sum Interrupt Enable (bit 3)
ICB 4
Timer X Interrupt Enable (bit 4)
ICB 5
Timer Y Interrupt Enable (bit 5)
ICB 6
Timer 1 Interrupt Enable ( bit 6)
ICB 7
Timer 2 Interrupt Enable (bit 7)
0: Interrupt Disable
1: Interrupt Enable
Address: 0006
16
Access:
R/W
Reset:
00
16
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