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參數(shù)資料
| 型號： | M37640E8FS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 24 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80 |
| 文件頁數(shù)： | 14/97頁 |
| 文件大小： | 1885K |
| 代理商： | M37640E8FS |
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20
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.14.1.4 Port P5
Port 5 is an 8-bit general purpose I/O port that can be
configured to access special second functions. The
port can be set up in any configuration in all three pro-
cessor modes.
Port P50
This pin is multiplexed with the XCin clock input.
When the XCin clock is activated, the pin’s I/O is dis-
abled.
Port P51
This pin is multiplexed with the XCout clock output
and the Timer 1/2 pulse output. When the XCin clock
is activated, the pin’s I/O is disabled. If XCin is not be-
ing used as a system clock or XCout oscillation is dis-
abled, the pin can be configured as the Timer 1/2
pulse output pin. This feature is configured in the
Timer123 mode register as described in section 1.17.
Port P52- P57
These pins are multiplexed with control pins for the
bus interface control block. P52 acts as OBF0 output
to a Master CPU when DBBC00 is “1”.
P53 acts as IBF0 output to a Master CPU when
DBBC01 is “1”.
P54-P57 act as input control signals from a Master
CPU when DBBC06 is “1”. The table featured in Fig-
ure 1.17 shows the bus interface control signal that
corresponds to each pin.
Fig. 1.17. Port P5 Block Diagram
Direction Register
Data Bus
Port Latch
CPMA4
XCin Input
Direction Register
Data Bus
Port Latch
Tout Enable Bit
Timer 1/2 Output
Direction Register
Data Bus
Port Latch
DBBC00
OBF0
Direction Register
Data Bus
Port Latch
DBBC01
IBF0
Port 54 - P57 Function
Pin
Function
P54
S0
P55
A0
P56
R(E)
P57
W(R/W)
Data Bus
Port Latch
see table
for function
Directi
Register
DBBC06
on
Port P50
Port P51
Port 52
Port P53
Port P54 - P57
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