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參數(shù)資料
| 型號： | M37560EFDFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100 |
| 文件頁數(shù)： | 29/92頁 |
| 文件大?。?/td> | 1507K |
| 代理商： | M37560EFDFP |
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
32
SERIAL I/O
Serial I/O1
Serial I/O1 can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer (baud rate generator) is
also provided for baud rate generation.
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O mode is selected by setting the se-
rial I/O1 mode selection bit of the serial I/O1 control register to “1”.
For clock synchronous serial I/O mode, the transmitter and the re-
ceiver must use the same clock as an operation clock.
When an internal clock is selected as an operation clock, transmit
or receive is started by a write signal to the transmit buffer regis-
ter.
When an external clock is selected as an operation clock, serial I/
O1 becomes the state where transmit or receive can be performed
by a write signal to the transmit buffer register. Transmit and re-
ceive are started by input of an external clock.
Fig. 28 Block diagram of clock synchronous serial I/O1
Fig. 29 Operation of clock synchronous serial I/O1 function
P46/SCLK1
P47/SRDY1
P44/RXD
P45/TXD
XIN
1/4
F/F
Serial I/O1 status register
Serial I/O1 control register
Receive buffer register
Address 001816
Receive shift register
Receive buffer full flag (RBF)
Receive interrupt request
Receive clock control circuit
Shift clock
Serial I/O1 synchronous
clock selection bit
Frequency division ratio 1/(n+1)
Baud rate generator
Address 001C16
BRG count source selection bit
Falling-edge detector
Data bus
Address 001816
Shift clock
Transmit shift register shift completion flag (TSC)
Transmit buffer empty flag (TBE)
Transmit interrupt request
Transmit interrupt source selection bit
Address 001916
Data bus
Address 001A16
Transmit buffer register
Transmit shift register
Transmit clock control circuit
Receive enable signal SRDY1
D7
D0
D1
D2
D3
D4
D5
D6
RBF = “1”
TSC = “1”
TBE = “0”
TBE = “1”
TSC = “0”
Transmit and receive shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TXD
Serial input RXD
Write signal to receive/transmit
buffer register (address 001816)
Overrun error (OE)
detection
Notes 1 : After data transferring, the TxD pin keeps D7 output value.
2 : If data is written to the transmit buffer register when TSC = “0”, the transmit clock is generated continuously and serial data can
be output continuously from the TXD pin.
3 : Select the serial I/O1 transmit interrupt request factor between when the transmit buffer register has emptied (TBE = “1”) or
after the transmit shift operation has ended (TSC = “1”), by setting the transmit interrupt source selection bit (TIC) of the serial
I/O1 control register.
4 : The serial I/O1 receive interrupt request occurs when the receive buffer full flag (RBF) becomes “1”.
D7
D0
D1
D2
D3
D4
D5
D6
(Note 1)
(Note 3)
(Note 2)
(Note 3)
(Note 4)
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