參數(shù)資料
型號(hào)： M37549G1-XXXFP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO24
封裝： 5.30 X 10.10 MM, 0.80 MM PITCH, PLASTIC, SSOP-24
文件頁數(shù)： 32/86頁
文件大小： 1375K
代理商： M37549G1-XXXFP
Rev.2.02
Mar 31, 2009
Page 36 of 81
REJ03B0202-0202
7549 Group
Serial Interface
Serial I/O
Serial I/O can be used as either clock synchronous or
asynchronous (UART) serial I/O. A dedicated timer is also
provided for baud rate generation.
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O mode can be selected by setting the
serial I/O mode selection bit of the serial I/O control register (bit
6) to “1”.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the TB/RB.
Fig 45. Block diagram of clock synchronous serial I/O
Fig 46. Operation of clock synchronous serial I/O function
Serial I/O control register
Receive buffer register 1
Receive shift register 1
Clock control circuit
1/4
Baud rate generator
φSOURCE
1/4
Clock control circuit
Falling-edge detector
Transmit buffer register
Transmit shift register
Serial I/O status register
F/F
Address 001816
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Shift clock
Serial I/O synchronous
clock selection bit
Frequency division ratio 1/(n+1)
Address 001C16
BRG count source selection bit
Address 001816
Shift clock
Transmit shift completion flag (TSC)
Transmit buffer empty flag (TBE)
Transmit interrupt request (TI)
Transmit interrupt source selection bit
Address 001916
Address 001A16
Data bus
P06/SCLK
P04/RXD
P05/TXD
P07/SRDY
D7
D0
D1
D2
D3
D4
D5
D6
D0
D1
D2
D3
D4
D5
D6
RBF = 1
TSC = 1
TBE = 0
TBE = 1
TSC = 0
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TxD
Serial input RxD
Write pulse to receive/transmit
buffer register 1 (address 001816)
Overrun error (OE)
detection
Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after
the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the
serial I/O control register.
2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial
data is output continuously from the TxD pin.
3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Receive enable signal SRDY
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