參數(shù)資料
型號: M37544G2GP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PQFP32
封裝: 7 X 7 MM, 0.80 MM PITCH, PLASTIC, LQFP-32
文件頁數(shù): 2/68頁
文件大?。?/td> 738K
代理商: M37544G2GP
7544 Group
Rev.1.04
2004.06.08
page 10 of 66
REJ03B0012-0104Z
Table 3 Push and pop instructions of accumulator or processor status register
Accumulator
Processor status register
Push instruction to stack
PHA
PHP
Pop instruction from stack
PLA
PLP
Fig. 10 Register push and pop at interrupt generation and subroutine call
Execute JSR
On-going Routine
M (S)
(PCH)
(S)
(S – 1)
M (S)
(PCL)
Execute RTS
(PCL)
M (S)
(S)
(S – 1)
(S)
(S + 1)
(S)
(S + 1)
(PCH)
M (S)
Subroutine
Restore Return
Address
Store Return Address
on Stack
M (S)
(PS)
Execute RTI
(PS)
M (S)
(S)
(S – 1)
(S)
(S + 1)
Interrupt
Service Routine
Restore Contents of
Processor Status Register
M (S)
(PCH)
(S)
(S – 1)
M (S)
(PCL)
(S)
(S – 1)
(PCL)
M (S)
(S)
(S + 1)
(S)
(S + 1)
(PCH)
M (S)
Restore Return
Address
I Flag “0” to “1”
Fetch the Jump Vector
Store Return Address
on Stack
Store Contents of Processor
Status Register on Stack
Interrupt request
(Note)
Note : The condition to enable the interrupt
Interrupt enable bit is “1”
Interrupt disable flag is “0”
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