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| 型號： | M37544G2ASP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP32 |
| 封裝： | 28 X 8.90 MM, 1.78 MM PITCH, PLASTIC, SDIP-32 |
| 文件頁數(shù)： | 66/77頁 |
| 文件大?。?/td> | 641K |
| 代理商： | M37544G2ASP |
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7544 Group (QzROM version)
REJ03B0108-0103
Rev.1.03
Mar 31, 2009
page 67 of 72
Termination of Unused Pins
1. Terminate unused pins
Perform the following wiring at the shortest possible distance (20
mm or less) from microcomputer pins.
(1) I/O ports
Set the I/O ports for the input mode and connect each pin to VCC
or VSS through each resistor of 1 k to 10 k. The port which can
select a built-in pull-up resistor can also use the built-in pull-up re-
sistor.
When using the I/O ports as the output mode, open them at “L” or
“H”.
When opening them in the output mode, the input mode of the
initial status remains until the mode of the ports is switched over
to the output mode by the program after reset. Thus, the poten-
tial at these pins is undefined and the power source current may
increase in the input mode. With regard to an effects on the sys-
tem, thoroughly perform system evaluation on the user side.
Since the direction register setup may be changed because of a
program runaway or noise, set direction registers by program
periodically to increase the reliability of program.
2. Termination remarks
(1) I/O ports setting as input mode
[1] Do not open in the input mode.
<Reason>
The power source current may increase depending on the first-
stage circuit.
An effect due to noise may be easily produced as compared with
proper termination (1) shown on the above “1. Terminate unused
pins”.
[2] Do not connect to VCC or VSS directly.
<Reason>
If the direction register setup changes for the output mode be-
cause of a program runaway or noise, a short circuit may occur.
[3] Do not connect multiple ports in a lump to VCC or VSS through
a resistor.
<Reason>
If the direction register setup changes for the output mode be-
cause of a program runaway or noise, a short circuit may occur
between ports.
Notes on Interrupts
1. Change of relevant register settings
When not requiring for the interrupt occurrence synchronous with
the following case, take the sequence shown in Figure 4.
When switching external interrupt active edge
When switching interrupt sources of an interrupt vector address
where two or more interrupt sources are allocated
Fig. 4 Sequence of changing relevant register
<Reason>
When setting the followings, the interrupt request bit of the corre-
sponding interrupt may be set to “1”.
When switching external interrupt active edge
INT0 interrupt edge selection bit
(bit 0 of Interrupt edge selection register (address 003A16))
INT1 interrupt edge selection bit
(bit 1 of Interrupt edge selection register)
CNTR0 active edge switch bit
(bit 2 of timer X mode register (address 002B16))
CNTR1 active edge switch bit
(bit 6 of timer A mode register (address 001D16))
2. Check of interrupt request bit
When executing the BBC or BBS instruction to determine an in-
terrupt request bit immediately after this bit is set to “0”, take the
following sequence.
<Reason>
If the BBC or BBS instruction is executed immediately after an in-
terrupt request bit is cleared to “0”, the value of the interrupt
request bit before being cleared to “0” is read.
Set the corresponding interrupt enable bit to “0” (disabled) .
↓
Set the interrupt edge selection bit, active edge switch bit, or
the interrupt source selection bit.
↓
NOP (One or more instructions)
↓
Set the corresponding interrupt request bit to “0”
(no interrupt request issued).
↓
Set the corresponding interrupt enable bit to “1” (enabled).
Set the interrupt request bit to “0” (no interrupt issued)
↓
NOP (one or more instructions)
↓
Execute the BBC or BBS instruction
Fig. 5 Sequence of check of interrupt request bit
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