參數(shù)資料
型號: M37544G2ASP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP32
封裝: 28 X 8.90 MM, 1.78 MM PITCH, PLASTIC, SDIP-32
文件頁數(shù): 16/77頁
文件大?。?/td> 641K
代理商: M37544G2ASP
7544 Group (QzROM version)
REJ03B0108-0103
Rev.1.03
Mar 31, 2009
page 21 of 72
Fig. 17 Interrupt control
Interrupt Disable Flag
The interrupt disable flag is assigned to bit 2 of the processor sta-
tus register. This flag controls the acceptance of all interrupt
requests except for the BRK instruction. When this flag is set to
“1”, the acceptance of interrupt requests is disabled. When it is set
to “0”, the acceptance of interrupt requests is enabled. This flag is
set to “1” with the SEI instruction and set to “0” with the CLI in-
struction.
When an interrupt request is accepted, the contents of the proces-
sor status register are pushed onto the stack while the interrupt
disable flag remains set to “0”. Subsequently, this flag is automati-
cally set to “1” and multiple interrupts are disabled.
To use multiple interrupts, set this flag to “0” with the CLI instruc-
tion within the interrupt processing routine.
The contents of the processor status register are popped off the
stack with the RTI instruction.
Interrupt Request Bits
Once an interrupt request is generated, the corresponding inter-
rupt request bit is set to “1” and remains “1” until the request is
accepted. When the request is accepted, this bit is automatically
set to “0”.
Each interrupt request bit can be set to “0”, but cannot be set to
“1”, by software.
Interrupt Enable Bits
The interrupt enable bits control the acceptance of the corre-
sponding interrupt requests. When an interrupt enable bit is set to
“0”, the acceptance of the corresponding interrupt request is dis-
abled. If an interrupt request occurs in this condition, the
corresponding interrupt request bit is set to “1”, but the interrupt
request is not accepted. When an interrupt enable bit is set to “1”,
the acceptance of the corresponding interrupt request is enabled.
Each interrupt enable bit can be set to “0” or “1” by software.
The interrupt enable bit for an unused interrupt should be set to
“0”.
Interrupt edge selection
The valid edge of external interrupt INT0 and INT1 can be selected
by the interrupt edge selection bit of the interrupt edge selection
register (003A16), respectively.
Key-on wakeup
Enable/disable of a key-on wakeup of pin P00 can be selected by
the key-on wakeup enable bit of the interrupt edge selection regis-
ter (003A16), respectively.
Interrupt disable flag I
Interrupt acceptance
Interrupt request bit
Interrupt enable bit
BRK instruction
Reset
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