參數(shù)資料
型號: M37542F8VGP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP32
封裝: 7 X 7 MM, 0.80 MM PITCH, PLASTIC, LQFP-32
文件頁數(shù): 42/139頁
文件大?。?/td> 1448K
代理商: M37542F8VGP
REVISION HISTORY
Rev.
Date
Description
Page
Summary
7542 Group Datasheet
2.03 Feb 10, 2004
2.04 Apr 14, 2004
2.05 Jun 08, 2004
2.06 Aug 24, 2004
Information about 36PJW-A package version added.
- Fig.4 Pin configuration added.
- Fig.9 Functional block diagram added.
- Table 1: Notes 2, 3 revised.
- 36PJW-A package added.
- Table 2 List of supported products revised.
- I/O Ports description and Fig. 19: Note revised.
- Table 5: Notes 2, 3 revised.
- INTEDGE revised.
- Fig.24: Note revised.
Table 12: P00–P03, P07 → P00–P03
Fig.100, Fig.101: td(CNVss-port) → th(CNVss-port)
Table 17: ICC data for FLASH ROM added.
Table 18: Absolute accuracy for FLASH ROM added.
Table 29: ICC data for FLASH ROM added.
Table 30: Absolute accuracy for FLASH ROM added.
Package: Description of 36PJW-A revised.
Table 2: M37542M2-XXXHP added.
Fig. 79, Fig. 80 a bit name revised.
Countermeasure against noise added.
(NOTES ON PERIPHERAL FUNCTIONS are included in APPENDIX at the end of
this data sheet.)
Part name revised.
36PJW-A package added.
APPENDIX added.
FEATURES Programmable I/O ports, A/D converter: Description added.
Fig.4: Pin 1 to Pin 3 revised. M37542F8HP: Note added.
Table 2: M37542F8HP: Note added.
Notes on A/D conversion added.
Table 7: Number of program/erase times revised.
Fig. 110: Figure title and table in figure revised, and Note added.
M37542F8HP: Note added.
Notes on A/D accuracy added.
Notes on Oscillation Stop Detection Circuit
1: Each bit of Port register Pi eliminated.
Note on Power Source Voltage added.
Words standardized: On-chip oscillator, A/D converter
Fig. 97: Bits 0 to 3 revised.
(1) ROM Code Protect Function: Some description added.
● Standard serial I/O Mode: Some description revised.
Description of standard serial I/O mode 1 and standard serial I/O mode 2 separated.
Fig. 107 Handling example of control pins in standard serial I/O mode 1 added.
Fig. 112 Handling example of control pins in standard serial I/O mode 2 added.
3
8
9
10
11
18
19
23
26
81
86
91
92
101
102
10
11
60
65 to 68
88
108
109 to 118
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3
11
53
70
88
89
117
119
All pages
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83 to 92
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