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參數(shù)資料
| 型號(hào)： | M37542F8VGP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP32 |
| 封裝： | 7 X 7 MM, 0.80 MM PITCH, PLASTIC, LQFP-32 |
| 文件頁(yè)數(shù)： | 39/139頁(yè) |
| 文件大?。?/td> | 1448K |
| 代理商： | M37542F8VGP |
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7542 Group
Rev.3.02
Oct 31, 2006
Page 133 of 134
REJ03B0006-0302
Notes on Clock Generating Circuit
1. Switch of ceramic and RC oscillations
After releasing reset, the oscillation mode selection bit (bit 5 of
CPU mode register (address 3B16)) is “0” (ceramic oscillation se-
lected). When the RC oscillation is used, after releasing reset, set
this bit to “1”.
2. Double-speed mode
The double-speed mode can be used only when a ceramic oscilla-
tion is selected. Do not use it when an RC oscillation is selected.
3. CPU mode register
Oscillation mode selection bit (bit 5), processor mode bits (bits 1
and 0) of CPU mode register (address 3B16) are used to select os-
cillation mode and to control operation modes of the
microcomputer. In order to prevent the dead-lock by erroneously
writing (ex. program run-away), these bits can be rewritten only
once after releasing reset. After rewriting, it is disabled to write any
data to the bit. (The emulator MCU “M37542RSS” is excluded.)
Also, when the read-modify-write instructions (SEB, CLB, etc.) are
executed to bits 2 to 4, 6 and 7, bits 5, 1 and 0 are locked.
4. Clock division ratio, XIN oscillation control, on-chip oscillator
control
The state transition shown in Fig. 81 can be performed by setting
the clock division ratio selection bits (bits 7 and 6), XIN oscillation
control bit (bit 4), on-chip oscillator oscillation control bit (bit 3) of
CPU mode register. Be careful of notes on use in Fig. 81.
5. On-chip oscillator operation
When the MCU operates by the on-chip oscillator for the main
clock, connect XIN pin to VCC through a 1 k to 10 k resistor and
leave XOUT pin open.
The clock frequency of the on-chip oscillator depends on the sup-
ply voltage and the operation temperature range.
Be careful that this margin of frequencies when designing applica-
tion products.
6. Ceramic resonator
When the ceramic resonator is used for the main clock, connect
the ceramic resonator and the external circuit to pins XIN and
XOUT at the shortest distance. Externally connect a damping resis-
tor Rd depending on the oscillation frequency. A feedback resistor
is built-in.
Use the resonator manufacturer’s recommended value because
constants such as capacitance depend on the resonator.
7. RC oscillation
When the RC oscillation is used for the main clock, connect the
XIN pin and XOUT pin to the external circuit of resistor R and the
capacitor C at the shortest distance.
The frequency is affected by a capacitor, a resistor and a micro-
computer.
So, set the constants within the range of the frequency limits.
8. External clock
When the external signal clock is used for the main clock, connect
the XIN pin to the clock source and leave XOUT pin open.
Select “0” (ceramic oscillation) to oscillation mode selection bit.
9. Count source (Timer 1, Timer A, Timer B, Timer X, Serial I/O,
Serial I/O2, A/D converter, Watchdog timer)
A count source of watchdog timer is affected by the clock divi-
sion selection bit of the CPU mode register.
The f(XIN) clock is supplied to the watchdog timer when select-
ing f(XIN) as the CPU clock.
The on-chip oscillator output is supplied to the watchdog timer
when selecting the on-chip oscillator output as the CPU clock.
Notes on Oscillation Control
1. Oscillation stop detection circuit
(1) When the stop mode is used, set the oscillation stop detection
function to “invalid”.
(2) When the ceramic or RC oscillation is stopped by the XIN oscil-
lation control bit (bit 4 of CPU mode register (address 3B16)),
set the oscillation stop detection function to “invalid”.
2. Stop mode
(1) When the stop mode is used, set the oscillation stop detection
function to “invalid”.
(2) When the stop mode is used, set “0” (STP instruction enabled)
to the STP instruction function selection bit of the watchdog
timer control register (bit 6 of watchdog timer control register
(address 3916)).
(3) The oscillation stabilizing time after release of STP instruction
can be selected from “set automatically ”/“not set automati-
cally” by the oscillation stabilizing time set bit after release of
the STP instruction (bit 0 of MISRG (address 3816)). When “0”
is set to this bit, “0116” is set to timer 1 and “FF16” is set to
prescaler 1 automatically at the execution of the STP instruc-
tion. When “1” is set to this bit, set the wait time to timer 1 and
prescaler 1 according to the oscillation stabilizing time of the
oscillation. Also, when timer 1 is used, set values again to
timer 1 and prescaler 1 after system is returned from the stop
mode.
(4) Do not execute the STP instruction during the A/D conversion.
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