參數資料
型號: M37542F8FP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, PDSO36
封裝: 0.450 INCH, PLASTIC, SSOP-36
文件頁數: 61/68頁
文件大?。?/td> 1191K
代理商: M37542F8FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7542 Group
MITSUBISHI MICROCOMPUTERS
64
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
s Notes on Clock Generating Circuit
For use with the oscillation stabilization set bit after release of the
STP instruction set to “1”, set values in timer 1 and prescaler 1 af-
ter fully appreciating the oscillation stabilization time of the
oscillator to be used.
Switch of ceramic and RC oscillations
After releasing reset the operation starts by starting a built-in ring
oscillator. Then, a ceramic oscillation or an RC oscillation is se-
lected by setting bit 5 of the CPU mode register.
Double-speed mode
When a ceramic oscillation is selected, a double-speed mode can
be used. Do not use it when an RC oscillation is selected.
CPU mode register
Bits 5, 1 and 0 of CPU mode register are used to select oscillation
mode and to control operation modes of the microcomputer. In or-
der to prevent the dead-lock by error-writing (ex. program
run-away), these bits can be rewritten only once after releasing re-
set. After rewriting it is disable to write any data to the bit. (The
emulator MCU “M37542RSS” is excluded.)
Also, when the read-modify-write instructions (SEB, CLB) are ex-
ecuted to bits 2 to 4, 6 and 7, bits 5, 1 and 0 are locked.
Clock division ratio, XIN oscillation control, ring oscillator control
The state transition shown in Fig. 79 can be performed by setting
the clock division ratio selection bits (bits 7 and 6), XIN oscillation
control bit (bit 4), ring oscillator oscillation control bit (bit 3) of CPU
mode register. Be careful of notes on use in Fig. 79.
s Notes on Ring Oscillation Division Ratio
When system is released from reset, ROSC/8 (ring middle-speed
mode) is selected for CPU clock.
When state transition from the ceramic or RC oscillation to ring oscil-
lator, ROSC/8 (ring middle-speed mode) is selected for CPU clock.
When the MCU operates by ring-oscillator for the main clock
without external oscillation circuit, connect XIN pin to VCC
through a resistor and leave XOUT pin open.
Set “10010x002” (x = 0 or 1) to CPUM.
s Notes on Oscillation Stop Detection Circuit
When the oscillation stop reset bit is set to “0”, internal reset
does not occur. If the ceramic or RC oscillation is selected for
the CPU clock, MCU will be locked when the ceramic or RC os-
cillation is stopped. So when the ceramic or RC oscillation is
selected for the main clock, set the oscillation stop reset bit to
“1”. (State 2’a of Fig. 81)
Ceramic or RC oscillation stop detection function active bit is not
cleared by the oscillation stop internal reset. Accordingly, the
oscillation stop detection circuit is in active when system is re-
leased from internal reset cause of oscillation stop detection.
Oscillation stop detection status bit is initialized by the following
operation.
(1) External reset
(2) Write “0” data to the ceramic or RC oscillation stop detection
function active bit.
The oscillation stop detection circuit is not included in the emu-
lator MCU “M37542RSS”.
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM produc-
tion:
1.Mask ROM Order Confirmation Form *
2.Mark Specification Form *
3.Data to be written to ROM, in EPROM form (three identical cop-
ies) or one floppy disk.
* For the mask ROM confirmation, ROM programming order con-
firmation and the mark specifications, refer to the “Mitsubishi
MCU Technical Information” Homepage
(http://www.infomicom.maec.co.jp/indexe.htm).
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