參數(shù)資料
型號(hào)： M37542F8FP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, PDSO36
封裝： 0.450 INCH, PLASTIC, SSOP-36
文件頁數(shù)： 32/68頁
文件大?。?/td> 1191K
代理商： M37542F8FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7542 Group
MITSUBISHI MICROCOMPUTERS
38
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
Input capture
7542 group has 2-input capture channels. Each channel (0 and 1)
has the same function and can be used to capture count value of
either Timer A or Timer B.
The source timer for each channel is selected by setting value of
the capture x (x = 0, 1) timer source bit. Timer A and Timer B can
be selected for the source timer to each channel, respectively.
To use each capture channel, set the capture x input port bits and
set the port direction register corresponding to capture channel to
input mode.
The input capture circuit retains the count value of selected timer
when external trigger is input. The timer count value is retained to
the capture latch x0 when rising edge is input and is retained to
the capture latch x1 when falling edge is input.
The count value of timer can be retained by software by capture y
(y = 00, 01, 10, 11) software trigger bit too. When “1” is set to this
bit, count value of timer is retained to the corresponded capture
latch.
When reading from the capture y software trigger bit is executed,
“0” is read out.
The latest status of capture latch can be confirmed by reading of
the capture x status bit. This bit indicates the capture latch which
latest data is in.
The valid trigger edge for capture interrupt is set by the capture x
interrupt edge selection bits. (Regardless of the setting value of
capture x interrupt edge selection bits, timer count values for both
edges are retained to the capture latch.)
Each capture input has the noise filter circuit that judges continu-
ous 4-time same level with sampling clock to be valid. The
sampling clock of noise filter is set by the capture x noise filter
clock selection bits.
Reading from the register for each channel is controlled by setting
value of the capture register read pointer. Reading from each reg-
ister is in the following order;
1.Set the value of the corresponded input capture channel to the
capture register read pointer.
2.Read from the capture register (low-order) and capture register
(high-order).
s Notes on Input Capture
If the capture trigger is input while the capture register (low-order
and high-order) is in read, captured value is changed between
high-order reading and low-order reading. Accordingly, some
countermeasure by software is recommended, for example
comparing the values that twice of read.
When the ring-oscillator is selected for Timer A count source,
Timer A cannot be used for the capture source timer.
Timer B cannot be used for the capture source timer when the
system is in the following state;
CPU operation clock source: XIN oscillation
Timer B count source: Timer A underflow
Timer A count source: Ring oscillator output
When writing “1” to capture latch x0 (x1) software trigger bit of
capture latch x0 and x1 at the same time, or external trigger and
software trigger occur simultaneously, the set value of capture x
status bit is undefined.
When setting the interrupt active edge selection bit and noise fil-
ter clock selection bit of external interrupt CAP0, CAP1, the
interrupt request bit may be set to “1”.
When not requiring the interrupt occurrence synchronized with
these setting, take the following sequence.
Set the corresponding interrupt enable bit to “0” (disabled).
Set the interrupt edge selection bit or noise filter clock selection bit.
Set the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
Set the corresponding interrupt enable bit to “1” (enabled).
The capture interrupt cannot be used as the interrupt for return
from stop mode. Even when the valid edge of the capture inter-
rupt is input at stop mode, system retains the stop mode. Then,
system returns from stop mode by other external interrupts, the
capture interrupt is accepted.
In this case, after system returns from stop mode, the interrupt
request bit of the corresponding capture interrupt is set to “1”.
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