參數(shù)資料
型號： M37542F8FP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, PDSO36
封裝： 0.450 INCH, PLASTIC, SSOP-36
文件頁數(shù)： 46/68頁
文件大小： 1191K
代理商： M37542F8FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7542 Group
MITSUBISHI MICROCOMPUTERS
50
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Transmit shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
Overrun error flag (OE)
0: No error
1: Overrun error
Parity error flag (PE)
0: No error
1: Parity error
Framing error flag (FE)
0: No error
1: Framing error
Summing error flag (SE)
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
Not used (returns “1” when read)
b7
Serial I/O2 status register
Serial I/O2 control register
b0
BRG count source selection bit (CSS)
0: f(XIN)
1: f(XIN)/4
Serial I/O2 synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous
serial I/O is selected, BRG output divided by 16
when UART is selected.
1: External clock input when clock synchronous serial
I/O is selected, external clock input divided by 16
when UART is selected.
SRDY2 output enable bit (SRDY)
0: P07 pin operates as ordinary I/O pin
1: P07 pin operates as SRDY2 output pin
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Serial I/O2 mode selection bit (SIOM)
0: Clock asynchronous (UART) serial I/O
1: Clock synchronous serial I/O
Serial I/O2 enable bit (SIOE)
0: Serial I/O2 disabled
(pins P04 to P07 operate as ordinary I/O pins)
1: Serial I/O2 enabled
(pins P04 to P07 operate as serial I/O pins)
b7
UART2 control register
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P05/TXD2 P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open drain output (in output mode)
Not used (return “1” when read)
b0
(SIO2STS : address 002F16, initial value: 8016)
(SIO2CON : address 003016, initial value: 0016)
(UART2CON : address 003116, initial value: E016)
Fig. 62 Structure of serial I/O2-related registers
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