參數(shù)資料
型號： M37274EFSP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 8.1 MHz, MICROCONTROLLER, PDIP52
封裝： 0.600 INCH, 1.78 MM PITCH, PLASTIC, SDIP-52
文件頁數(shù)： 114/148頁
文件大小： 1946K
代理商： M37274EFSP
67
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37274EFSP
PRELIMINARY
Notice:
This
is not
a final
specification.
Some
paramentic
limits
are
subject
to change.
MITSUBISHI MICROCOMPUTERS
Fig. 65. Block Control Registers
Fig. 64. OSD Control Register
b7 b6 b5 b4 b3 b2 b1 b0
OSD control register (OC) [Address 00CE16]
B
Name
Functions
After reset R W
OSD Control Register
0
OSD control bit
(OC0) (See note 1)
0 : All-blocks display off
1 : All-blocks display on
0
1
Scan mode selection
bit (OC1)
0 : Normal scnan mode
1 : Bi-scan mode
0
2
0 : All bordered
1 : Shadow bordered (See note 2)
0
4
Automatic solid space
control bit (OC4)
0
Border type selection
bit (OC2)
RW
3
0 : Color signal of character background
part does not flash
1 : Color signal of character background
part flashes
Flash mode selection
bit (OC3)
6, 7 Layer mixing control
bits (OC6, OC7)
(See note 3)
0 0: Logic sum (OR) of layer 1’s
color and layer 2’s color
0 1: Layer 1’s color has priority
1 0: Layer 2’s color has priority
1 1: Do not set.
b7 b6
0 : OFF
1 : ON
0R W
5
Window control bit
(OC5)
0R W
0 : OFF
1 : ON
Notes 1 : Even this bit is switched during display, the display screen
remains unchanged until a rising (falling) of the next V SYNC.
2 : Shadow border is output at right and bottom side of the font.
3 : Set “00” during displaying extra fonts.
b7 b6 b5 b4 b3 b2 b1 b0
Block control register i (BCi) (i=1 to 16) [Addresses 00D016 to 00DF16](See note 1)
Block Control register i
0, 1 Display mode
selection bits
(BCi0, BCi1)
Indeterminate
3, 4 Dot size selection
bits (BCi3, BCi4)
5, 6 Pre-divide ratio
layer selection bit
(BCi5, BCi6)
7
OUT2 output control bit
(BCi7) (See note 2)
b1
b0
0
0: Display OFF
0
1: OSD mode
1
0: CC mode
1
1: EXOSD mode
BC17: Window top boundary
BC27: Window bottom boundary
B
Name
Functions
After reset
RW
Indeterminate RW
2
Border control bit
(BCi2)
0: Border OFF
1: Border ON
Indeterminate RW
Notes 1: Note that MASK version the block control registers at addresses 00D0 16 to 00DB16
when programming.
2: Bit 4 of the color code 1 controls OUT1 output when bit 7 is "0".
Bit 4 of the color code 1 controls OUT2 output when bit 7 is "1".
3: CS6 : Bit 6 of the clock control register (address 0216 16)
4: Tc : Pre-devided clock period for OSD
5: H : Hsync
b6
b5
b4
b3
CS6 Pre-divide
Dot size
Display
layer
ratio
0
1
0
1
0
1
—
0
1
0
1
0
1
! 1
! 2
! 3
! 1
! 2
1Tc ! 1/2H
1Tc ! 1H
2Tc ! 2H
3Tc ! 3H
1Tc ! 1/2H
1Tc ! 1H
2Tc ! 2H
3Tc ! 3H
1Tc ! 1/2H
1Tc ! 1H
2Tc ! 2H
3Tc ! 3H
1Tc ! 1/2H
1Tc ! 1H
1Tc ! 1/2H
1Tc ! 1H
1.5Tc ! 1/2H
1.5Tc ! 1H
0
1
Layer1
Layer2
—
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
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