參數(shù)資料
型號(hào): M37274EFSP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 8.1 MHz, MICROCONTROLLER, PDIP52
封裝: 0.600 INCH, 1.78 MM PITCH, PLASTIC, SDIP-52
文件頁數(shù): 107/148頁
文件大小: 1946K
代理商: M37274EFSP
60
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37274EFSP
PRELIMINARY
Notice:
This
is not
a final
specification.
Some
paramentic
limits
are
subject
to change.
(6) START Condition Generation Method
When the ESO bit of the I2C control register (address 00F916) is “1,”
execute a write instruction to the I2C status register (address 00F816)
to set the MST, TRX and BB bits to “1.” A START condition will then
be generated. After that, the bit counter becomes “0002” and an SCL
for 1 byte is output. The START condition generation timing and BB
bit set timing are different in the standard clock mode and the high-
speed clock mode. Refer to Figure 58 for the START condition gen-
eration timing diagram, and Table 8 for the START condition/STOP
condition generation timing table.
Fig. 57. Interrupt Request Signal Generation Timing
SCL
PIN
IICIRQ
Fig. 58. START Condition Generation Timing Diagram
(7) RESTART Condition Generation Method
To generate the RESTART condition, take the following sequence:
1Set “2016” to the I2C status register (S1).
2Write a transmit data to the I2C data shift register.
3Set “F016” to the I2C status register (S1) again.
<Example of Setting of RESTART Condition>
I2C status register
; S1 = 2016
I2C data shift register ; S0 = transmit data after restart
I2C status register
; S1 = F016
I2C status register
write signal
Set time for
BB flag
Hold time
Setup
time
SCL
SDA
BB flag
Setup
time
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