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參數(shù)資料
| 型號： | M37274EFSP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 8.1 MHz, MICROCONTROLLER, PDIP52 |
| 封裝： | 0.600 INCH, 1.78 MM PITCH, PLASTIC, SDIP-52 |
| 文件頁數(shù)： | 101/148頁 |
| 文件大小： | 1946K |
| 代理商： | M37274EFSP |
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55
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37274EFSP
PRELIMINARY
Notice:
This
is not
a final
specification.
Some
paramentic
limits
are
subject
to change.
(3) I2C Clock Control Register
The I2C clock control register (address 00FA16) is used to set ACK
control, SCL mode and SCL frequency.
s Bits 0 to 4: SCL Frequency Control Bits (CCR0–CCR4)
These bits control the SCL frequency. Refer to Table 7.
s Bit 5: SCL Mode Specification Bit (FAST MODE)
This bit specifies the SCL mode. When this bit is set to “0,” the stan-
dard clock mode is set. When the bit is set to “1,” the high-speed
clock mode is set.
s Bit 6: ACK Bit (ACK BIT)
This bit sets the SDA status when an ACK clock
V is generated. When
this bit is set to “0,” the ACK return mode is set and SDA goes to
LOW at the occurrence of an ACK clock. When the bit is set to “1,”
the ACK non-return mode is set. The SDA is held in the HIGH status
at the occurrence of an ACK clock.
However, when the slave address matches the address data in the
reception of address data at ACK BIT = “0,” the SDA is automatically
made LOW (ACK is returned). If there is a mismatch between the
slave address and the address data, the SDA is automatically made
HIGH (ACK is not returned).
VACK clock: Clock for acknowledgement
b7 b6 b5 b4 b3 b2 b1 b0
I2C clock control register (S2 : address 00FA16)
I2C Clock Control Register
0
to
4
SCL frequency control bits
(CCR0 to CCR4)
7
5
6
SCL mode
specification bit
(FAST MODE)
0 : Standard clock mode
1 : High-speed clock mode
0
Standard clock
mode
B
Name
Functions
After reset RW
0
ACK bit
(ACK BIT)
ACK clock bit
(ACK)
0 : ACK is returned.
1 : ACK is not returned.
0 : No ACK clock
1 : ACK clock
High speed
clock mode
Setup disabled Setup disabled
00 to 02
Setup disabled
333
03
Setup disabled
250
04
100
400 (See note)
05
83.3
166
06
500/CCR value
1000/CCR value
...
17.2
34.5
1D
16.6
33.3
1E
16.1
32.3
1F
(at
φ = 4 MHz, unit : kHz)
Note: At 4000kHz in the high-speed clock mode, the duty is as below .
“0” period : “1” period = 3 : 2
In the other cases, the duty is as below.
“0” period : “1” period = 1 : 1
Setup value of
CCR4–CCR0
RW
Fig. 53. I2C Address Register
s Bit 7: ACK Clock Bit (ACK)
This bit specifies a mode of acknowledgment which is an acknowl-
edgment response of data transmission. When this bit is set to “0,”
the no ACK clock mode is set. In this case, no ACK clock occurs
after data transmission. When the bit is set to “1,” the ACK clock
mode is set and the master generates an ACK clock upon comple-
tion of each 1-byte data transmission.The device for transmitting
address data and control data releases the SDA at the occurrence of
an ACK clock (make SDA HIGH) and receives the ACK bit gener-
ated by the data receiving device.
Note: Do not write data into the I2C clock control register during trans-
mission. If data is written during transmission, the I2C clock
generator is reset, so that data cannot be transmitted nor-
mally.
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