參數(shù)資料
型號： M37271MF-XXXSP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
中文描述： 單芯片8位CMOS微機隱蔽字幕解碼器和屏幕顯示控制器
文件頁數(shù)： 33/97頁
文件大小： 1436K
代理商： M37271MF-XXXSP
MITSUBISHI MICROCOMPUTERS
M37271MF-XXXSP
M37271EF-XXXSP, M37271EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
33
2
Selection of field to be sliced data
In the case of the main data slice line, the field to be sliced data is
selected by bits 2 and 1 of the data slicer control register 1 (address
00EA
16
). In the case of the sub-data slice line, the field is selected
by bits 2 and 1 of the data slicer control register 3. When bit 2 of
the data slicer control register 1 is set to “1,” it is possible to slice
data of both fields (refer to Figure 23).
3
Specification of line to set slice voltage
The reference voltage for slicing (slice voltage) is generated by
integrating the amplitude of the clock run-in pulse in the particular
line (refer to Table 3).
4
Field determination
The field determination flag can be read out by bit 5 of the data
slicer control register 1. This flag charge at the falling edge of
V
sep
.
Fig. 27. Signals in vertical blanking interval
(5) Data Slice Line Specification Circuit
1
Specification of data slice line
M37271MF-XXXSP has 2 data slice line specification circuits for
slicing arbitrary 2 H
sep
in 1 field. The following 2 data slice lines
are specified .
<Main data slice line>
This line is specified by the caption position register (address
00E0
16
).
<Sub-data slice line>
This line is specified by the data slicer control register 3 (address
00EB
16
).
The counter is reset at the falling edge of V
sep
and is incremented
by 1 every H
sep
pulse. When the counter value matched the value
specified by bits 4 to 0 of the caption position register (in case of
the sub-data slice line, by bits 3 to 7 of the data slicer control register
3), this H
sep
is sliced.
The values of “00
16
” to “1F
16
” can be set in the caption position
register. Bit 7 to bit 5 are used for testing. Set “100
2
.” Figure 27
shows the signals in the vertical blanking interval. Figure 28 shows
the structure of the caption position register.
Line
Line specified by bits 4 to 0 of CP
(Main data slice line)
Line specified by bits 7 to 3 of DSC3
(Sub-data slice line)
Table 3. Specifying of field whose sets reference voltage
Bit 0 of DSC3
DSC1 : Data slice control register 1
DSC3 : Data slice control register 3
CP : Caption position register
Field
Field specified by bit 1 of DSC1
0: F2
1: F1
Field specified by bit 1 of DSC3
0: F2
1: F1
0
1
Video signal
Vertical blanking interval
Composite
video signal
Count value to be set in the caption position register (“11
16
” in this case)
H
sep
V
sep
H
sep
Magnified
drawing
Clock run-in
Start bit + 16-bit data
Start bit
Time to be set in the
start bit position register
Composite video
signal
min. max.
Line 21
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