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參數(shù)資料
| 型號： | M37271MF-XXXSP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER |
| 中文描述： | 單芯片8位CMOS微機隱蔽字幕解碼器和屏幕顯示控制器 |
| 文件頁數(shù)： | 16/97頁 |
| 文件大?。?/td> | 1436K |
| 代理商： | M37271MF-XXXSP |
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MITSUBISHI MICROCOMPUTERS
M37271MF-XXXSP
M37271EF-XXXSP, M37271EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
16
(9)Timer 5 · 6 interrupt
An interrupt is generated by an overflow of timer 5 or 6. Their
priorities are same, and can be switched by software.
(10)BRK instruction interrupt
This software interrupt has the least significant priority. It does
not have a corresponding interrupt enable bit, and it is not af-
fected by the interrupt disable flag I (non-maskable).
Fig. 8. Structure of interrupt-related registers
Fig. 9. Interrupt control
Interrupt request bit
Interrupt enable bit
Interrupt disable flag I
BRK instruction
Reset
Interrupt
request
7
Interrupt request register 1
(IREQ1: address 00FC
16
)
Timer 1 interrupt request bit
0
Timer 2 interrupt request bit
Timer 3 interrupt request bit
Timer 4 interrupt request bit
OSD interrupt request bit
V
SYNC
interrupt request bit
A-D conversion
INT3 interrupt
request bit
Multi-master I
2
C-BUS
interface interrupt request bit
Timer 5
6 interrupt request bit
Fix this bit to “0.”
0 : No interrupt request issued
1 : Interrupt request issued
7
Interrupt request register 2
(IREQ2: address 00FD
16
)
INT1 interrupt request bit
0
Data slicer interrupt request bit
Serial I/O interrupt request bit
INT2 interrupt request bit
0
0 : Interrupt disabled
1 : Interrupt enabled
7
Interrupt control register 2
( ICON2 : address 00FF
16
)
INT1 interrupt enable bit
0
Data slicer interrupt enable bit
Serial I/O interrupt enable bit
7
Interrupt control register 1
( ICON1: address 00FE
16
)
Timer 1 interrupt enable bit
0
Timer 2 interrupt enable bit
Timer 3 interrupt enable bit
Timer 4 interrupt enable bit
OSD interrupt enable bit
V
SYNC
interrupt enable bit
A-D conversion
INT3 interrupt
request bit
f(X
IN
)/4096 interrupt request bit
Multi-master I
2
C-BUS
interface enable bit
Timer 5
6 interrupt enable bit
Timer 5
6 interrupt switch bit
0 : Timer 5
1 : Timer 6
INT2 interrupt enable bit
f(X
IN
)/4096 interrupt enable bit
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