參數(shù)資料
型號(hào)： M37271MF-XXXSP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
中文描述： 單芯片8位CMOS微機(jī)隱蔽字幕解碼器和屏幕顯示控制器
文件頁(yè)數(shù)： 21/97頁(yè)
文件大?。?/td> 1436K
代理商： M37271MF-XXXSP
MITSUBISHI MICROCOMPUTERS
M37271MF-XXXSP
M37271EF-XXXSP, M37271EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
21
Fig. 14. Structure of serial I/O mode register
Internal clock—the serial I/O counter is set to “7” during write cycle
into the serial I/O register (address 0214
16
), and transfer clock goes
“H” forcibly. At each falling edge of the transfer clock after the write
cycle, serial data is output from the S
OUT
pin. Transfer direction can
be selected by bit 5 of the serial I/O mode register. At each rising
edge of the transfer clock, data is input from the S
IN
pin and data in
the serial I/O register is shifted 1 bit.
After the transfer clock has counted 8 times, the serial I/O counter
becomes “0” and the transfer clock stops at “H.” At this time the inter-
rupt request bit is set to “1.”
External clock—when an external clock is selected as the clock
source, the interrupt request is set to “1” after the transfer clock has
counted 8 times. However, transfer operation does not stop, so con-
trol the clock externally. Use the external clock of 500kHz or less
with a duty cycle of 50%.
The serial I/O timing is shown in Figure 13. When using an external
clock for transfer, the external clock must be held at “H” for initializing
the serial I/O counter. When switching between an internal clock and
an external clock, do not switch during transfer. Also, be sure to ini-
tialize the serial I/O counter after switching.
Notes 1:
On programming, note that the serial I/O counter is set by
writing to the serial I/O register with the bit managing in-
structions as SEB and CLB instructions.
2:
When an external clock is used as the synchronizing clock,
write transmit data to the serial I/O register at “H” of the
transfer clock input level.
Fig. 13. Serial I/O timing (for LSB first)
7
Serial I/O mode register
(SM : address 0213
16
)
Internal synchronizing clock
selection bits
b1 b0
0 0 : f(X
IN
)/8 or f(X
CIN
)/8
0 1 : f(X
IN
)/16 or f(X
CIN
)/16
1 0 : f(X
IN
)/32 or f(X
CIN
)/32
1 1 : f(X
IN
)/64 or f(X
CIN
)/64
0
0
Synchronizing clock selection bit
0 : External clock
1 : Internal clock
Port function selection bit
0 : P1
1
, P1
3
functions as port
1 : SCL1, SDA1
Port function selection bit
0 : P1
2
, P1
4
functions as port
1 : SCL2, SDA2
Transfer direction selection bit
0 : LSB first
1 : MSB first
Fix these bits to “0”
0
Synchroninzing clock
Transfer clock
Serial I/O register
write signal
Serial I/O output
S
OUT
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
(Note)
Serial I/O input
S
IN
Note :
When an internal clock is selected, the S
OUT
pin is at high-impedance after transfer is completed.
Interrupt request bit is set to “1”
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