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參數(shù)資料
| 型號： | M37271MF-231SP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER |
| 中文描述： | 單芯片8位CMOS微機隱蔽字幕解碼器和屏幕顯示控制器 |
| 文件頁數(shù)： | 27/97頁 |
| 文件大?。?/td> | 1436K |
| 代理商： | M37271MF-231SP |
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MITSUBISHI MICROCOMPUTERS
M37271MF-XXXSP
M37271EF-XXXSP, M37271EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
27
V
REF
256
(n – 0.5)
1
to
255
0
0
Note:
V
REF
indicates the voltage of internal V
CC
.
Fig. 20. Changes in A-D conversion register and comparison voltage during A-D conversion
(6) Conversion Method
1
Set bit 7 of the interrupt interval determination control register (ad-
dress 0212
16
) to “1” to generate an interrupt request at comple-
tion of A-D conversion.
2
Set the A-D conversion · INT3 interrupt request bit to “0” (even
when A-D conversion is started, the A-D conversion · INT3 inter-
rupt bit is not set to “0” automatically).
3
When using A-D conversion interrupt, enable interrupts by setting
A-D conversion · INT3 interrupt request bit to “1” and setting the
interrupt disable flag to “0.”
4
Set the V
CC
connection selection bit to “1” to connect V
CC
to the
resistor ladder.
5
Select analog input pins by setting the analog input selection bit of
the A-D control register.
6
Set the A-D conversion completion bit to “0.” This write operation
starts the A-D conversion. Do not read the A-D conversion regis-
ter during the A-D conversion.
7
Verify the completion of the conversion by the state (“1”) of the
A-D conversion completion bit, that (“1”) of A-D conversion · INT3
interrupt bit, or the occurrence of an A-D conversion interrupt.
8
Read the A-D conversion register to obtain the conversion results.
Note :
When the ladder resistor is disconnect from V
CC
, set the V
CC
connection selection bit to “0” between steps
7
and
8
.
(7) Internal Operation
At the time when the A-D conversion starts, the following operations
are automatically performed.
1
The A-D conversion register is set to “00
16
.”
2
The most significant bit of the A-D conversion register becomes
“1, ” and the comparison voltage “V
ref
” is input to the comparator.
At this point, V
ref
is compared with the analog input voltage “V
IN
.”
3
Bit 7 is determined by the comparison result as follows.
When V
ref
< V
IN
: bit 7 holds “1”
When V
ref
> V
IN
: bit 7 becomes “0”
With the above operations, the analog value is converted into a digi-
tal value. The A-D conversion terminates in a maximum 50 machine
cycles (12.5
μ
s at f(X
IN
) = 8 MHz) after it starts, and the conversion
result is stored in the A-D conversion register.
An A-D conversion interrupt request occurs at the same time of A-D
conversion completion, the A-D conversion · INT3 interrupt request
bit becomes “1.” The A-D conversion completion bit also becomes
“1.”
Table 2. Expression for V
ref
and V
REF
A-D conversion register contents “n”
(decimal notation)
V
ref
(V)
1 2
3 4 5 6
Digital value corresponding to
analog input voltage.
7 8
1 0 0 0 0
0 0
0
1 2
1 0 0
0 0
0
1 0
0 0
0 0
0
1
1 2
3 4 5
6
7
1
V
REF
2
V
REF
2
V
REF
2
V
REF
512
V
REF
4
V
REF
4
V
REF
512
V
REF
8
V
REF
512
0 0 0 0 0
0 0
0
Contents of A-D conversion register
Reference voltage (V
ref
)
[V]
0
A-D conversion start
1st comparison start
3rd comparison start
8th comparison start
2nd comparison start
A-D conversion completion
(8th comparison completion)
V
REF
2
V
REF
4
.......
V
REF
8
V
REF
256
±
±
±
V
REF
512
–
±
: Value determined by mth (m = 1 to 8) result
m
.....
–
±
±
–
±
–
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