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參數(shù)資料
| 型號(hào)： | M37271MF-231SP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER |
| 中文描述： | 單芯片8位CMOS微機(jī)隱蔽字幕解碼器和屏幕顯示控制器 |
| 文件頁(yè)數(shù)： | 12/97頁(yè) |
| 文件大小： | 1436K |
| 代理商： | M37271MF-231SP |
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MITSUBISHI MICROCOMPUTERS
M37271MF-XXXSP
M37271EF-XXXSP, M37271EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
12
Fig. 5. Memory map of special function register 2 (SFR2) (1)
210
16
211
16
212
16
213
16
214
16
215
16
216
16
217
16
218
16
219
16
21A
16
21B
16
21C
16
21D
16
21E
16
21F
16
200
16
201
16
202
16
203
16
204
16
205
16
206
16
207
16
208
16
209
16
20A
16
PWM mode register 1 (PN)
PWM mode register 2 (PW)
20B
16
20C
16
20D
16
20E
16
20F
16
Timer 5 (TM5)
Timer 6 (TM6)
Sync pulse counter register (SYC)
Data slicer control register 3 (DSC3)
PWM2 register (PWM2)
PWM3 register (PWM3)
PWM6 register (PWM6)
PWM4 register (PWM4)
PWM5 register (PWM5)
PWM0 register (PWM0)
PWM1 register (PWM1)
Interrupt interval determination register (RI)
Interrupt interval determination control register (RE)
Serial I/O mode register (SM)
Serial I/O register (SIO)
Clock source control register (CS)
I/O polarity control register (PC)
Extra font color register (EC)
Window H register 1 (WH1)
Window L register 1 (WH1)
Window H register 2 (WH2)
Window L register 2 (WH2)
Clock run-in detect register (CRD3)
Clock run-in register (CR3)
Border color register (FC)
b7
b0
SYC0
FC2
b7
b0
07
16
FF
16
0
0
00
16
0
0
0
0
00
16
0
0
0
0
0
0
0
0
0
Raster color register (RC)
00
16
0
PW0
PW1
PW2
PW3
PW4
PW5
PW6
ENABLE
POL
SYC1
SYC2
SYC3
SYC4
SYC5
DSC30
DSC31
DSC32
DSC37
DSC35
RE0
RE1
RE2
RE3
RE4
RE5
POL
INT3
POL
SEL
AD/INT3
SEL
INT3
AD/INT3
SM0
RE1
SM1
RE2
SM2
RE3
SM3
SM4
RE5
SM5
PC0
RE1
PC1
RE2
PC2
RE3
PC3
PC4
RE5
PC5
INT3
POL
AD/INT3
SEL
AD/INT3
SEL
AD/INT3
SEL
PC6
RE1
CS1
RE2
CS2
RE3
CS3
RE5
CS5
AD/INT3
SEL
CS0
CS4
CS6
RC0
RE1
RC1
RE2
RC2
RE3
RC3
RC4
RE5
RC5
RC6
RE1
RE2
RE3
RE5
FC0
FC1
FC3
FC4
WH20
WH21
WL20
WL21
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DSC36
DSC34DSC33
0
0
0
0
0
0
0
CRD31
CRD32
CRD33
CRD34
CRD35
0
0
0
0
0
0
0
0
1
: “1” immediately after reset
: Fix this bit to “0” ( do not write “1”)
: “0” immediately after reset
: Nothing is allocated
I
SFR2 area (addresses 200
16
to 21F
16
)
Address
Register
: undefined immediately after reset
Bit allocation
State immediately after reset
0
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