參數(shù)資料
型號: M37271EF-XXXSP
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
中文描述: 單芯片8位CMOS微機(jī)隱蔽字幕解碼器和屏幕顯示控制器
文件頁數(shù): 76/97頁
文件大?。?/td> 1436K
代理商: M37271EF-XXXSP
MITSUBISHI MICROCOMPUTERS
M37271MF-XXXSP
M37271EF-XXXSP, M37271EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
76
INTERRUPT INTERVAL DETERMINATION
FUNCTION
The M37271MF-XXXSP incorporates an interrupt interval determi-
nation circuit. This interrupt interval determination circuit has an 8-bit
binary up counter as shown in Figure 86. Using this counter, it deter-
mines an interval or a pulse width on the INT1 or INT2 (refer to Fig-
ure 88).
The following describes how the interrupt interval is determined.
1. The determination mode is selected by using bit 5 of the interrupt
interval determination control register (address 0212
16
). When this
bit is set to “0,” the interrupt interval determination mode is se-
lected; when the bit is set to “1,” the pulse width determination
mode is selected.
2. The interrupt input to be determined (INT1 input or INT2 input) is
selected by using bit 2 in the interrupt interval determination con-
trol register (address 0212
16
). When this bit is cleared to “0,” the
INT1 input is selected ; when the bit is set to “1,” the INT2 input is
selected.
3. When the INT1 input is to be determined, the polarity is selected
by using bit 3 of the interrupt interval determination control
register ; when the INT2 input is to be determined, the polarity is
selected by using bit 4 of the interrupt interval determination
control register.
When the relevant bit is cleared to “0,” determination is made of
the interval of a positive polarity (rising transition) ; when the bit is
set to “1,” determination is made of the interval of a negative po-
larity (falling transition).
4. The reference clock is selected by using bit 1 of the interrupt inter-
val determination control register. When the bit is cleared to “0,” a
32
μ
s clock is selected ; when the bit is set to “1,” a 16
μ
s clock is
selected (based on an oscillation frequency of 8MHz in either case).
5. Simultaneously when the input pulse of the specified polarity
(rising or falling transition) occurs on the INT1 pin (or INT2 pin),
the 8-bit binary up counter starts counting up with the selected
reference clock (32
μ
s or 16
μ
s).
6. Simultaneously with the next input pulse, the value of the 8-bit
binary up counter is loaded into the interrupt interval determina-
tion register (address 0211
16
) and the counter is immediately re-
set (“00
16
”). The reference clock is input in succession even after
the counter is reset, and the counter restarts counting up from
“00
16
”.
7. When count value “FE
16
” is reached, the 8-bit binary up counter
stops counting. Then, simultaneously when the next reference
clock is input, the counter sets value “FF
16
” to the interrupt inter-
val determination register. The reference clock is generated by
setting bit 0 of the PWM mode register 1 to “0.”
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