參數(shù)資料
型號(hào)： M37271EF-XXXSP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
中文描述： 單芯片8位CMOS微機(jī)隱蔽字幕解碼器和屏幕顯示控制器
文件頁(yè)數(shù)： 39/97頁(yè)
文件大?。?/td> 1436K
代理商： M37271EF-XXXSP
MITSUBISHI MICROCOMPUTERS
M37271MF-XXXSP
M37271EF-XXXSP, M37271EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
39
Function
In conformity with Philips I
2
C-BUS
standard:
10-bit addressing format
7-bit addressing format
High-speed clock mode
Standard clock mode
In conformity with Philips I
2
C-BUS
standard:
Master transmission
Master reception
Slave transmission
Slave reception
16.1 kHz to 400 kHz (at
φ
= 4 MHz)
Table 6. Multi-master I
2
C-BUS interface functions
Item
Format
Communication mode
SCL clock frequency
φ
System clock = f(X
IN
)/2
Note:
We are not responsible for any third party’s infringement of
patent rights or other rights attributable to the use of the con-
trol function (bits 6 and 7 of the I
2
C control register at address
00F9
16
) for connections between the I
2
C-BUS interface and
ports (SCL1, SCL2, SDA1, SDA2).
MULTI-MASTER I
2
C-BUS INTERFACE
The multi-master I
2
C-BUS interface is a circuit for serial communica-
tions conformed with the Philips I
2
C-BUS data transfer format. This
interface, having an arbitration lost detection function and a synchro-
nous function, is useful for serial communications of the multi-mas-
ter.
Figure 39 shows a block diagram of the multi-master I
2
C-BUS inter-
face and Table 6 shows multi-master I
2
C-BUS interface functions.
This multi-master I
2
C-BUS interface consists of the I
2
C address reg-
ister, the I
2
C data shift register, the I
2
C clock control register, the I
2
C
control register, the I
2
C status register and other control circuits.
Fig. 39. Block diagram of multi-master I
2
C-BUS interface
I C address register
b7
b0
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1SAD0 RBW
Noise
elimination
circuit
Serial
data
(SDA)
Address comparator
b7
I C data shift register
b0
Data
control
circuit
I C clock control register
System clock
(
φ
)
Interrupt
generating
circuit
Interrupt
request signal
(IICIRQ)
b7
MST TRX BB
PIN
AL AAS AD0 LRB
b0
I C status
register
S1
b7
b0
BSEL1
BSEL0
10BIT
SAD
ALS
BC2 BC1 BC0
S1D I C clock control register
Bit counter
BB
circuit
Clock
control
circuit
Noise
elimination
circuit
Serial
clock
(SCL)
b7
ACKBIT
b0
FAST
Internal data bus
Clock division
S
0
S2
S0D
AL
circuit
ES0
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