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參數(shù)資料
| 型號： | M37271EF-XXXSP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER |
| 中文描述： | 單芯片8位CMOS微機隱蔽字幕解碼器和屏幕顯示控制器 |
| 文件頁數(shù)： | 11/97頁 |
| 文件大小： | 1436K |
| 代理商： | M37271EF-XXXSP |
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MITSUBISHI MICROCOMPUTERS
M37271MF-XXXSP
M37271EF-XXXSP, M37271EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
11
Fig. 4. Memory map of special function register 1 (SFR2) (2)
F0
16
F1
16
F2
16
F3
16
F4
16
F5
16
F6
16
F7
16
F8
16
F9
16
FA
16
FB
16
FC
16
FD
16
FE
16
FF
16
E0
16
E1
16
E2
16
E3
16
E4
16
E5
16
E6
16
E7
16
E8
16
E9
16
EA
16
EB
16
EC
16
ED
16
EE
16
EF
16
Data slicer control register 1 (DSC1)
Data slicer control register 2 (DSC2)
Data register 3 (CD3)
Data register 4 (CD4)
A-D conversion register (AD)
A-D control register (ADCON)
Timer 1 (TM1)
Timer 2 (TM2)
Timer 3 (TM3)
Timer 4 (TM4)
Timer mode register 1 (TM1)
Timer mode register 2 (TM2)
I
2
C
data shift register (S0)
I
2
C
address register (S0D)
Window register (WN)
Sync slice register (SSL)
Clock run-in register 1 (CR1)
Clock run-in register 2 (CR2)
Clock run-in detect register 1 (CRD1)
Clock run-in detect register 2 (CRD2)
Data register 1 (CD1)
Data register 2 (CD2)
Caption position register (CP)
Start bit position register (SP)
I
2
C
control register (S1D)
I
2
C
clock control register (S2)
CPU mode
register (CPUM)
Interrupt request
register 1 (IREQ1)
Interrupt request
register 2 (IREQ2)
Interrupt control
register 1 (ICON1)
Interrupt control
register 2 (ICON2)
b7
b0
ADIN0
ADIN1
ADVREF
ADSTR
ADV
TM20
TM21
TM22
TM23
TM24
TM10
TM11
TM12
TM13
TM14
CM2
TM1R
TM2R
TM3R
TM4R
CRTR
VSCR
ADR
INT2R
INT1R
DSR
SIOR
TM1E
TM2E
TM3E
TM4E
CRTE
VSCE
INT1E
DSE
SIOE
INT2E
TM25
b7
b0
CK0
0
00
16
00
16
0
0
FF
16
07
16
FF
16
07
16
0
0
00
16
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
1
0
0
1
I
2
C
status register (S1)
0
0
0
0
0
0
0
TM15
TM16
TM17
TM26
TM27
SAD0
SAD1
SAD2
SAD3
SAD4
SAD5
SAD6
RBW
LRB
AD0
AAS
AL
PIN
BB
10 BIT
SAD
FAST
MODE
CM5
TRX
MST
BC0
BC1
BC2
ES0
ALS
BSEL0
ACK
BIT
CM6
BSEL1
CCR0
CCR1
CCR2
CCR3
CCR4
ACK
00
16
00
16
0
0
0
0
0
0
1MSR
IICR
T56R
ADE
1MSE
IICE
T56E
T56S
CM0
CM1
CM7
DSC20
DSC21
DSC22
DSC25
DSC27
DSC10
DSC11
DSC12
DSC15
DSC17
0
0
0
0
0
0
1
1
SSL7
1
0
0
00
16
0
CP0
SP0
WN0
CP1
SP1
WN1
CP2
SP2
WN2
CP3
SP3
WN3
CP4
SP4
WN4
SP5
WN5
SP6
SP7
0
0
0
0
0
0
0
CRD20
CRD21
CRD22
CRD25
CRD27CRD25
CRD25CRD25
1
0
0
0
0
1
0
1
0
1
0
1
0
0
0
CR21
CR11
0
1
0
0
1
0
0
0
0
CRD10
CRD11
CRD12
CRD15
CRD17CRD15
CRD15CRD15
1
: “1” immediately after reset
: Fix this bit to “0” ( do not write “1”)
: Nothing is allocated
I
SFR1 area (addresses E0
16
to FF
16
)
Address
Register
: undefined immediately after reset
Bit allocation
State immediately after reset
: Fix this bit to “1” ( do not write “0”)
: “0” immediately after reset
0
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