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參數(shù)資料
| 型號(hào)： | M37270MF-XXXSP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.1 MHz, MICROCONTROLLER, PDIP64 |
| 封裝： | 0.750 INCH, 1.78 MM PITCH, PLASTIC, SDIP-64 |
| 文件頁數(shù)： | 50/97頁 |
| 文件大?。?/td> | 1359K |
| 代理商： | M37270MF-XXXSP |
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MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
51
Notes 1 : 1TC (TC : OSD clock cycle divided by prescaler) gap oc-
curs between the horizontal display start position set by
the horizontal position register and the most left dot of the
1st block. Accordingly, when 2 blocks have different pre-
divide ratios, their horizontal display start position will not
match.
2 : The horizontal start position is based on the OSD clock
source cycle selected for each block. Accordingly, when 2
blocks have different OSD clock source cycles, their hori-
zontal display start position will not match.
Fig. 57. Notes on horizontal display start position
(3) Dot Size
The dot size can be selected by a block unit. The dot size in vertical
direction is determined by dividing HSYNC in the vertical dot size con-
trol circuit. The dot size in horizontal is determined by dividing the
following clock in the horizontal dot size control circuit : the clock
gained by dividing the OSD clock source (data slicer clock, OSC1) in
the pre-divide circuit. The clock cycle divided in the pre-divide circuit
is defined as 1TC.
The dot size of the layer 1 is specified by bits 6 to 3 of the block
control register.
The dot size of the layer 2 is specified by the following bits : bits 3
and 4 of the block control register, bit 6 of the clock source control
register. Refer to Figure 50 (the structure of the block control regis-
ter), refer to Figure 59 (the structure of the clock source control reg-
ister).
The block diagram of dot size control circuit is shown in Figure 58.
Notes 1 : The pre-divide ratio = 3 cannot be used in the CC mode.
2 : The pre-divide ratio of the OSD mode block on the layer 2
must be same as that of the CC mode block on the layer 1
by bit 6 of the clock source control register.
3 : In the bi-scan mode, the dot size in the vertical direction is
2 times as compared with the normal mode. Refer to “(13)
Scan Mode” about the scan mode.
Fig. 58. Block diagram of dot size control circuit
HSYNC
1TC
Block 1 (Pre-divide ratio = 1, clock source = data slicer clock)
1TC
4TOSC!N
4TOSC’!N
Note 1
Note 2
Block 2 (Pre-divide ratio = 2, clock source = data slicer clock)
Block 3 (Pre-divide ratio = 3, clock source = data slicer clock)
Block 4 (Pre-divide ratio = 3, clock source = OSC1)
Data slicer clock
HSYNC
OSC1
CS0
Synchronization
Cycle!2
circuit
Cycle!3
Pre-divide circuit
Clock cycle
= 1TC
Horizontal dot size
control circuit
Vertical dot size
control circuit
OSD control circuit
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| M37272E8SP | 8-BIT, OTPROM, 8.1 MHz, MICROCONTROLLER, PDIP42 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M37271EF | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER |
| M37271EFSP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER |
| M37271EFSS | 功能描述:EPROM MCU/8BIT CMOS EMULATION CH RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 配件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 附件類型:適配器板 適用于相關(guān)產(chǎn)品:RCB230，RCB231，RCB212 配用:26790D-ND - RCB BREAKOUT BOARD RS232 CABLE |
| M37271EF-XXXSP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER |
| M37271MF | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER |
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