參數(shù)資料
型號(hào): M37225ECSP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 8.1 MHz, MICROCONTROLLER, PDIP42
封裝: 0.600 INCH, 1.78 MM PITCH, PLASTIC, SDIP-42
文件頁數(shù): 80/128頁
文件大?。?/td> 1481K
代理商: M37225ECSP
M37225M6/M8/MA/MC-XXXSP, M37225ECSP
Rev.1.00
Nov 01, 2000
page 53 of 124
REJ03B0136-0100Z
Fig. 8.9.2 ROM Correction Enable Register
Fig. 8.9.1 ROM Correction Address Registers
8.9 ROM CORRECTION FUNCTION
This can correct program data in ROM. Up to 3 addresses can be
corrected, a program for correction is stored in the ROM correction
vector in RAM as the top address. The ROM correction vectors are 3
vectors.
Vector 1 : address 02C016
Vector 2 : address 02E016
Vector 3 : address 030016
Set the address of the ROM data to be corrected into the ROM cor-
rection address register. When the value of the counter matches the
ROM data address in the ROM correction vector as the top address,
the main program branches to the correction program stored in the
ROM memory for correction. To return from the correction program
to the main program, the op code and operand of the JMP instruction
(total of 3 bytes) are necessary at the end of the correction program.
The ROM correction function is controlled by the ROM correction
enable register.
Notes 1: Specify t he first address (op code address) of each
instruction as the ROM correction address.
2: Use the JMP instruction (total of 3 bytes) to return from
the correction program to the main program.
3: Do not set the same ROM correction address to vectors 1 to 3.
021716
ROM correction address 1 (high-order)
021816
ROM correction address 1 (low-order)
021916
ROM correction address 2 (high-order)
021A16
ROM correction address 2 (low-order)
021C16
ROM correction address 3 (high-order)
021D16
ROM correction address 3 (low-order)
b7 b6 b5 b4 b3 b2 b1 b0
ROM correction enable register (RCR) [Address 021B16]
B
After reset RW
ROM Correction Enable Register
0
Vector 1 enable bit (RCR0)
Name
Functions
0: Disabled
1: Enabled
0
RW
1
Vector 2 enable bit (RCR1)
0: Disabled
1: Enabled
0
RW
0
3
to
7
Fix these bits to “0.”
0
RW
0
2
Vector 3 enable bit (RCR2)
0: Disabled
1: Enabled
0
RW
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