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參數(shù)資料
| 型號(hào)： | M37225ECSP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 8.1 MHz, MICROCONTROLLER, PDIP42 |
| 封裝： | 0.600 INCH, 1.78 MM PITCH, PLASTIC, SDIP-42 |
| 文件頁(yè)數(shù)： | 64/128頁(yè) |
| 文件大?。?/td> | 1481K |
| 代理商： | M37225ECSP |
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M37225M6/M8/MA/MC-XXXSP, M37225ECSP
Rev.1.00
Nov 01, 2000
page 38 of 124
REJ03B0136-0100Z
(8) Bit 7: Communication mode specification bit
(master/slave specification bit: MST)
This bit is used for master/slave specification for data communica-
tion. When this bit is “0,” the slave is specified, so that a START
condition and a STOP condition generated by the master are received,
and data communication is performed in synchronization with the
clock generated by the master. When this bit is “1,” the master is
specified and a START condition and a STOP condition are gener-
ated, and also the clocks required for data communication are gen-
erated on the SCL.
The MST bit is cleared to “0” in one of the following conditions.
Immediately after completion of 1-byte data transmission when
arbitration lost is detected
When a STOP condition is detected.
When occurence of a START condition is disabled by the START
condition duplication preventing function (Note).
At reset
Fig. 8.6.7 I2C Status Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C status register (S1) [Address 00D916]
I2C Status Register
0
3
4
5
6, 7
b7 b6
0
0 : Slave recieve mode
0
1 : Slave transmit mode
1
0 : Master recieve mode
1
1 : Master transmit mode
1
2
0
1
0
B
Name
Functions
After reset R W
Communication mode
specification bits
(TRX, MST)
0 : Bus free
1 : Bus busy
Bus busy flag (BB)
0 : Interrupt request issued
1 : No interrupt request issued
I2C-BUS interface interrupt
request bit (PIN)
0 : Not detected
1 : Detected
Arbitration lost detecting flag
(AL) (See note)
0 : Address mismatch
1 : Address match
Slave address comparison
flag (AAS) (See note)
0 : No general call detected
1 : General call detected
General call detecting flag
(AD0) (See note)
0 : Last bit = “0 ”
1 : Last bit = “1 ”
Last receive bit (LRB)
(See note)
Note : These bits and flags can be read out, but cannnot be written.
Indeterminate R —
R —
R W
0
R W
(See note)
Fig. 8.6.8 Interrupt Request Signal Generation Timing
SCL
PIN
IICIRQ
Note: The START condition duplication prevention function disables the START
condition generation, reset of bit counter reset, and SCL output, when
the following condition is satisfied:
a START condition is set by another master device.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M37225M6 | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SNGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER |
| M37225M8 | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SNGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER |
| M37225MA | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SNGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER |
| M372429100 | 制造商:ITW Switches 功能描述:IN-RUSH |
| M372429200 | 制造商:ITW Switches 功能描述:IN-RUSH |
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