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參數(shù)資料
| 型號： | M37161MA-XXXSP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP42 |
| 封裝： | 0.600 INCH, 1.78 MM PITCH, PLASTIC, SDIP-42 |
| 文件頁數(shù)： | 65/129頁 |
| 文件大?。?/td> | 1092K |
| 代理商： | M37161MA-XXXSP |
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Rev.1.00
2003.11.25
page 40 of 128
M37161M8/MA/MF-XXXSP/FP,M37161EFSP/FP
Fig. 8.6.13 Address Data Communication Format
SSlave address
A
DataA
DataA/A
P
R/W
7 bits
“0”
1 to 8 bits
SSlave address
A
Data
AData
A
P
7 bits
“1”
1 to 8 bits
(1) A master-transmitter transmits data to a slave-receiver
S
Slave address
1st 7 bits
A
Data
7 bits
“0”
8 bits
1 to 8 bits
(2) A master-receiver receives data from a slave-transmitter
Slave address
2nd byte
A
DataA/A
P
1 to 8 bits
S
Slave address
1st 7 bits
A
7 bits
“0”
8 bits
7 bits
(3) A master-transmitter transmits data to a slave-receiver with a 10-bit address
Slave address
2nd byte
Data
1 to 8 bits
Sr
Slave address
1st 7 bits
A
Data
A
P
1 to 8 bits
“1”
(4) A master-receiver receives data from a slave-transmitter with a 10-bit address
S: START conditionP : STOP condition
A: ACK bitR/W : Read/Write bit
Sr: Restart condition
From master to slave
From slave to master
R/W
8.6.12 Precautions when using multi-master
I2C-BUS interface
(1) Read-modify-write instruction
Precautions for executing the read-modify-write instructions such as
SEB and CLB, is executed for each register of the multi-master I2C-
BUS interface are described below.
I2C data shift register (S0)
When executing the read-modify-write instruction for this register
during transfer, data may become an arbitrary value.
I2C address register (S0D)
When the read-modify-write instruction is executed for this register
at detection of the STOP condition, data may become an arbitrary
______
value because hardware changes the read/write bit (RBW) at the
above timing.
I2C status register (S1)
Do not execute the read-modify-write instruction for this register
because all bits of this register are changed by hardware.
I2C control register (S1D)
When the read-modify-write instruction is executed for this register
at detection of the START condition of the byte transfer, data may
become an arbitrary value because hardware changes the bit
counter (BC0–BC2) at the above timing.
I2C clock control register (S2)
The read-modify-write instruction can be executed for this register.
(2) START condition generation procedure us-
ing multi-master
Procedure example (The necessary conditions for the procedure
are described in to below).
LDA
—
(Take out of slave address value)
SEI
(Interrupt disabled)
BBS 5,S1,BUSBUSY
(BB flag confirmation and branch process)
BUSFREE:
STA S0
(Write slave address value)
LDM #$F0, S1
(Trigger START condition generation)
CLI
(Interrupt enabled)
BUSBUSY:
CLI
(Interrupt enabled)
Use “STA,” “STX” or “STY” of the zero page addressing instruc-
tion for writing the slave address value to the I2C data shift register.
Use “LDM” instruction for setting trigger of START condition gen-
eration.
Write the slave address value of and set trigger of START con-
dition generation as in continuously, as shown in the procedure
example.
Disable interrupts during the following three process steps:
BB flag confirmation
Write slave address value
Trigger of START condition generation
When the condition of the BB flag is bus busy, enable interrupts
immediately.
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PDF描述 |
|---|---|
| M37161M8-XXXSP | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP42 |
| M37202E3SP | 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PDIP64 |
| M37207EFFP | 8-BIT, OTPROM, 8.1 MHz, MICROCONTROLLER, PQFP80 |
| M37207MF-XXXSP | 8-BIT, MROM, 8.1 MHz, MICROCONTROLLER, PDIP64 |
| M37207M8-XXXSP | 8-BIT, MROM, 8.1 MHz, MICROCONTROLLER, PDIP64 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M37161MF-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37161MF-XXXSP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M3720 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1 KEY 1 SOUND |
| M3720-1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1 KEY 1 SOUND |
| M3720-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1 KEY 1 SOUND |
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