參數資料
型號： M36W832Be85ZA1S
廠商： 意法半導體
英文描述： 32 Mbit 2Mb x16, Boot Block Flash Memory and 8 Mbit 512Kb x16 SRAM, Multiple Memory Product
中文描述： 32兆位的2Mb x16插槽，引導塊閃存和8兆位的SRAM 512KB的x16，內存產品多
文件頁數： 8/64頁
文件大小： 897K
代理商： M36W832BE85ZA1S
M36W832TE, M36W832BE
8/64
Signal Descriptions
See Figure 2 Logic Diagram and Table 1,Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A18).
Addresses
are common inputs for the Flash and the SRAM
components. The Address Inputs select the cells
in the memory array to access during Bus Read
operations. During Bus Write operations they con-
trol the commands sent to the Command Interface
of the internal state machine. The Flash memory is
accessed through the Chip Enable (
EF
) and Write
Enable (WF) signals, while the SRAM is accessed
through two Chip Enable signals (E1S and E2S)
and the Write Enable signal (WS).
Address Inputs (A19-A20).
Addresses A19-A20
are inputs for the Flash component only. The
Flash memory is accessed through the Chip En-
able (EF) and Write Enable (WF) signals
Data Input/Output (DQ0-DQ15).
The Data I/O
outputs the data stored at the selected address
during a Bus Read operation or inputs a command
or the data to be programmed during a Write Bus
operation.
Flash Chip Enable (EF).
The Chip Enable input
activates the Flash memory control logic, input
buffers, decoders and sense amplifiers. When
Chip Enable is at V
IL
and Reset is at V
IH
the device
is in active mode. When Chip Enable is at V
IH
the
memory is deselected, the outputs are high imped-
ance and the power consumption is reduced to the
standby level.
Flash Output Enable (GF).
The Output Enable
controls the data outputs during the Bus Read op-
eration of the Flash memory.
Flash Write Enable (
WF
).
The
controls the Bus Write operation of the Flash
memory’s Command Interface. The data and ad-
dress inputs are latched on the rising edge of Chip
Enable, EF, or Write Enable, WF, whichever oc-
curs first.
Flash Write Protect (WPF).
Write Protect is an
input that gives an additional hardware protection
for each block. When Write Protect is at V
IL
, the
Lock-Down is enabled and the protection status of
the block cannot be changed. When Write Protect
is at V
IH
, the Lock-Down is disabled and the block
can be locked or unlocked. (refer to Table 6, Read
Protection Register and Protection Register Lock).
Flash Reset (RPF).
The Reset input provides a
hardware reset of the Flash memory. When Reset
is at V
IL
, the memory is in reset mode: the outputs
are high impedance and the current consumption
is minimized. After Reset all blocks are in the
Locked state. When Reset is at V
IH
, the device is
in normal operation. Exiting reset mode the device
enters read array mode, but a negative transition
A0-A18
Write
Enable
of Chip Enable or a change of the address is re-
quired to ensure valid data outputs.
SRAM Chip Enable (E1S, E2S).
The Chip En-
able inputs activate the SRAM memory control
logic, input buffers and decoders. E1S at V
IH
or
E2S at V
IL
deselects the memory and reduces the
power consumption to the standby level. E1S and
E2S can also be used to control writing to the
SRAM memory array, while WS remains at V
IL.
It
is not allowed to set EF at V
IL,
E1S at V
IL
and E2S
at V
IH
at the same time.
SRAM Write Enable (WS).
The Write Enable in-
put controls writing to the SRAM memory array.
WS is active low.
SRAM Output Enable (GS).
The Output Enable
gates the outputs through the data buffers during
a read operation of the SRAM memory. GS is ac-
tive low.
SRAM Upper Byte Enable (UBS).
The
Byte Enable enables the upper bytes for SRAM
(DQ8-DQ15). UBS is active low.
SRAM Lower Byte Enable (LBS).
The
Byte Enable enables the lower bytes for SRAM
(DQ0-DQ7). LBS is active low.
V
DDF
Supply Voltage (2.7V to 3.3V).
V
DDF
pro-
vides the power supply to the internal core of the
Flash Memory device. It is the main power supply
for all operations (Read, Program and Erase).
V
DDQF
and V
DDS
Supply Voltage (2.7V to 3.3V).
V
DDQF
provides the power supply for the Flash
memory I/O pins and V
DDS
provides the power
supply for
the SRAM control pins. This allows all
Outputs to be powered independently of the Flash
core power supply, V
DDF
. V
DDQF
can be tied to
V
DDS
V
PPF
Program Supply Voltage.
V
PPF
is both a
control input and a power supply pin for the Flash
memory. The two functions are selected by the
voltage range applied to the pin. The Supply Volt-
age V
DDF
and the Program Supply Voltage V
PPF
can be applied in any order.
If V
PPF
is kept in a low voltage range (0V to 3.6V)
V
PPF
is seen as a control input. In this case a volt-
age lower than V
PPLK
gives an absolute protection
against program or erase, while V
PPF
> V
PP1
en-
ables these functions (see Table 15, DC Charac-
teristics for the relevant values). V
PPF
is only
sampled at the beginning of a program or erase; a
change in its value after the operation has started
does not have any effect on Program or Erase,
however for Double or Quadruple Word Program
the results are uncertain.
If V
PPF
is in the range 11.4V to 12.6V it acts as a
power supply pin. In this condition V
PPF
must be
stable until the Program/Erase algorithm is com-
pleted (see Table 17 and 18).
Upper
Lower
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