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參數(shù)資料
| 型號： | M36P0R9070E0ZACE |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 512 Mbit (x16, Multiple Bank, Multi-Level, Burst) Flash Memory 128 Mbit (Burst) PSRAM, 1.8V Supply, Multi-Chip Package |
| 中文描述： | 512兆位（x16插槽，多銀行，多層次，多突發(fā)）128兆位閃存（突發(fā)）移動存儲芯片，1.8V電源，多芯片封裝 |
| 文件頁數(shù)： | 10/26頁 |
| 文件大?。?/td> | 200K |
| 代理商： | M36P0R9070E0ZACE |
2 Signal descriptions
M36P0R9070E0
10/26
2.5
Wait (WAIT)
WAIT is an output pin common to the Flash memory and PSRAM components. However the
WAIT signal does not behave in the same way for the PSRAM and the Flash memory.
For details of how it behaves, please refer to the M69KB128AA datasheet for the PSRAM and
to the M58PR512J datasheet for the Flash memory.
2.6
Flash Chip Enable input (E
F
)
The Flash Chip Enable input activates the control logic, input buffers, decoders and sense
amplifiers of the Flash memory component selected. When Chip Enable is Low, V
IL
, and
Reset
is High, V
IH
, the device is in active mode. When Chip Enable is at V
IH
the corresponding Flash
memory are deselected, the outputs are high impedance and the power consumption is
reduced to the standby level.
It is not allowed to have E
F
at V
IL
and E
P
at V
IL
at the same time. Only one memory component
can be enabled at a time.
2.7
Flash Output Enable inputs (G
F
)
The Output Enable pins control the data outputs during Flash memory Bus Read operations.
2.8
Flash Write Enable (W
F
)
The Write Enable controls the Bus Write operation of the Flash memory Command Interface.
The data and address inputs are latched on the rising edge of Chip Enable or Write Enable
whichever occurs first.
2.9
Flash Write Protect (WP
F
)
Write Protect is an input that gives an additional hardware protection for each block. When
Write Protect is Low, V
IL
, Lock-Down is enabled and the protection status of the Locked-Down
blocks cannot be changed. When Write Protect is at High, V
IH
, Lock-Down is disabled and the
Locked-Down blocks can be locked or unlocked. (See the Lock Status Table in the M58PR512J
datasheet).
2.10 Flash Reset (RP
F
)
The Reset input provides a hardware reset of the Flash memories. When Reset is at V
IL
, the
memory is in Reset mode: the outputs are high impedance and the current consumption is
reduced to the Reset Supply Current I
DD2
. Refer to
Table 7., Flash Memory DC Characteristics
- Currents
, for the value of I
DD2
. After Reset all blocks are in the Locked state and the
Configuration Register is reset. When Reset is at V
IH
, the device is in normal operation. Exiting
Reset mode the device enters Asynchronous Read mode, but a negative transition of Chip
Enable or Latch Enable is required to ensure valid data outputs.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M36P0R9070E0ZACF | 制造商:Micron Technology Inc 功能描述:WIRELESS - Tape and Reel |
| M36P0R9070E1ZACE | 制造商:Micron Technology Inc 功能描述:WIRELESS - Trays |
| M36P0R9070E1ZACF | 制造商:Micron Technology Inc 功能描述:WIRELESS - Tape and Reel |
| M36P0R9070N1ZSE | 制造商:Micron Technology Inc 功能描述:WIRELESS - Trays |
| M36P0R9070N1ZSF | 制造商:Micron Technology Inc 功能描述:WIRELESS - Tape and Reel |
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