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參數(shù)資料
| 型號(hào)： | M35080BN |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | EEPROM |
| 英文描述： | 8 Kbit Serial SPI Bus EEPROM With Incremental Registers |
| 中文描述： | 8千位串行SPI總線的EEPROM與增量寄存器 |
| 文件頁數(shù)： | 11/18頁 |
| 文件大小： | 139K |
| 代理商： | M35080BN |
11/18
M35080
POWER ON STATE
After power-on, the memory device is in the follow-
ing state:
– low power stand-by state
– deselected (after power-on, a high-to-low transi-
tion is required on the S input before any opera-
tions can be started).
– the WEL bit is reset
– the SRWD, BP1 and BP0 bits of the status reg-
ister are unchanged from the previous power-
down (they are non-volatile bits).
INITIAL DELIVERY STATE
The device is delivered with the memory array in a
fully erased state. With the exception of the first 32
bytes, all data bits are set to ‘1’, and hence all data
bytes are at FFh. The first 32 bytes are set to all
‘0’s, and hence the first 16 words at 0000h.
The status register bits are initialized to ‘0’, except
for bit b4, which is set to ‘1’, as shown in Table 8.
Figure 12. Page Write Operation Sequence
Note: 1. The most significant address bits, A15-A10, are treated as Don’t Care.
2. The number of clock pulses must be a multiple of 8. Otherwise, the write is aborted.
C
D
AI01796
S
34
33
35 36 37 38 39 40 41 42
44 45 46 47
32
C
D
S
15
2
1
3
4
5
6
7
8
9 10
20 21 22 23 24 25 26 27
14 13
3
2
1
0
28 29 30
INSTRUCTION
16 BIT ADDRESS
0
7
6
5
4
3
2
0
1
DATA BYTE 1
31
43
7
6
5
4
3
2
0
1
DATA BYTE 2
7
6
5
4
3
2
0
1
DATA BYTE 3
6
5
4
3
2
0
1
DATA BYTE N
Table 8. Initial Status Register Format
b7
b0
0
0
0
1
0
0
0
0
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