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參數資料
| 型號： | M35080-MN6T |
| 廠商： | 意法半導體 |
| 元件分類： | EEPROM |
| 英文描述： | 8 Kbit Serial SPI Bus EEPROM With Incremental Registers |
| 中文描述： | 8千位串行SPI總線的EEPROM與增量寄存器 |
| 文件頁數： | 1/18頁 |
| 文件大小： | 139K |
| 代理商： | M35080-MN6T |
1/18
PRELIMINARY DATA
June 1999
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M35080
8 Kbit Serial SPI Bus EEPROM
With Incremental Registers
I
Compatible with SPI Bus Serial Interface
(Positive Clock SPI Modes)
I
Single Supply Voltage: 4.5 V to 5.5 V
I
5 MHz Clock Rate (maximum)
I
Sixteen 16-bit Incremental Registers
I
BYTE and PAGE WRITE (up to 32 Bytes)
(except for the Incremental Registers)
I
Self-Timed Programming Cycle
I
Hardware Protection of the Status Register
I
Resizeable Read-Only EEPROM Area
I
Enhanced ESD Protection
I
1 Million Erase/Write Cycles (minimum)
I
40 Year Data Retention (minimum)
DESCRIPTION
The M35080 device consists of 1024x8 bits of low
power
EEPROM,
STMicroelectronics’ proprietary High Endurance
Double Polysilicon CMOS technology.
The device is accessed by a simple SPI-compati-
ble serial interface. The bus signals consist of a
serial clock input (C), a serial data input (D) and a
serial data output (Q), as shown in Table 1.
The device is selected when the chip select input
(S) is held low. Data is clocked in during the low to
high transition of the clock, C. Data is clocked out
during the high to low transition of the clock.
fabricated
with
Figure 1. Logic Diagram
AI02143
S
VCC
M35080
VSS
W
Q
C
D
Table 1. Signal Names
C
Serial Clock
D
Serial Data Input
Q
Serial Data Output
S
Chip Select
W
Write Protect
V
CC
Supply Voltage
V
SS
Ground
PSDIP8 (BN)
0.25 mm frame
SO8 (MN)
150 mil width
8
1
8
1
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